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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. rev.2.41 jan 10, 2006 page 1 of 96 rej03b0001-0241 m16c/62p group (m16c/62p, m16c/62pt) single-chip 16-bit cmos microcomputer rej03b0001-0241 rev.2.41 jan 10, 2006 1. overview the m16c/62p group (m16c/62p, m16c/62pt) of single-chip microcomputers are built using the high performance silicon gate cmos process using a m 16c/60 series cpu core and are packaged in a 80-pin, 100-pin and 128-pin plastic molded qfp. these single-chip mi crocomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m byte s of address space, they are capable of executing instructions at high speed. in addition, this microcomputer contains a multiplier and dmac which combined with fast instruction processing capability, makes it suitable for control of various oa, co mmunication, and industrial equipment which requires high- speed arithmetic/logic operations. 1.1 applications audio, cameras, television, home applia nce, office/communications/portable /industrial equipm ent, automobile, etc. specifications written in this ma nual are believed to be accurate, but are not guarante ed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 2 of 96 rej03b0001-0241 1.2 performance outline table 1.1 to 1.3 list performance outline of m16c /62p group (m16c/62p, m16c/62pt)(128-pin version). notes: 1. i 2 c bus is a registered trademark of koninklijke philips electronics n. v. 2. iebus is a registered trademark of nec electronics corporation. 3. see table 1.8 product code for the program and erase endurance, and operating ambient temperature. in addition 1,000 times/10,000 times ar e under development as of jul., 2005. please inquire about a release schedule. 4. all options are on request basis. table 1.1 performance outline of m16c/62p gr oup (m16c/62p, m16c/62pt)(128-pin version) item performance m16c/62p cpu number of basic inst ructions 91 instructions minimum instruction execution time 41.7ns(f(bclk)=24mhz, vcc1=3.3 to 5.5v) 100ns(f(bclk)=10mhz, vcc1=2.7 to 5.5v) operating mode single-chip, memory expansion and microprocessor mode address space 1 mbyte (available to 4 mbytes by memory space expansion function) memory capacity see table 1.4 to 1.5 product list peripheral function port input/output : 113 pins, input : 1 pin multifunction timer timer a : 16 bits x 5 channels, timer b : 16 bits x 6 channels, three phase motor control circuit serial interface 3 channels clock synchronous, uart, i 2 c bus (1) , iebus (2) 2 channels clock synchronous a/d converter 10-bit a/d converter: 1 circuit, 26 channels d/a converter 8 bits x 2 channels dmac 2 channels crc calculation circuit ccitt-crc watchdog timer 15 bits x 1 channel (with prescaler) interrupt internal: 29 sources, external: 8 sources, software: 4 sources, priority level: 7 levels clock generation circuit 4 circuits main clock generation circuit (*), subclock generation circuit (*), on-chip oscillator, pll synthesizer (*)equipped with a built-in feedback resistor. oscillation stop detection function stop detection of main clock oscillation, re-oscillation detection function voltage detection circuit available (option (4) ) electric characteristics supply voltage vcc1=3.0 to 5.5 v, vcc2=2.7v to vcc1 (f(bclk=24mhz) vcc1=2.7 to 5.5 v, vcc2=2.7v to vcc1 (f(bclk=10mhz) power consumption 14 ma (vcc1=vcc2=5v, f(bclk)=24mhz) 8 ma (vcc1=vcc2=3v, f(bclk)=10mhz) 1.8 a (vcc1=vcc2=3v, f(xcin)=32khz, wait mode) 0.7 a (vcc1=vcc2=3v, stop mode) flash memory version program/erase supply volt age 3.30.3 v or 5.00.5 v program and erase endurance 100 times (all area) or 1,000 times (user rom area without block a and block 1) / 10,000 times (block a, block 1) (3) operating ambient temperature -20 to 85 c, -40 to 85 c (3) package 128-pin plastic mold lqfp m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 3 of 96 rej03b0001-0241 notes: 1. i 2 c bus is a registered trademark of koninklijke philips electronics n. v. 2. iebus is a registered trademark of nec electronics corporation. 3. see table 1.8 and 1.9 product code for the program and erase end urance, and operating ambient temperature. in addition 1,000 times/10,000 times ar e under development as of jul., 2005. please inquire about a release schedule. 4. use the m16c/62pt on vcc1=vcc2 5. all options are on request basis. table 1.2 performance outline of m16c/62p gr oup (m16c/62p, m16c/62pt)(100-pin version) item performance m16c/62p m16c/62pt (4) cpu number of basic instructions 91 instructions minimum instruction execution time 41.7ns(f(bclk)=24mhz, vcc1=3.3 to 5.5v) 100ns(f(bclk)=10mhz, vcc1=2.7 to 5.5v) 41.7ns(f(bclk)=24mhz, vcc1=4.0 to 5.5v) operating mode single-chip, memory expansion and microprocessor mode single-chip address space 1 mbyte (available to 4 mbytes by memory space expansion function) 1 mbyte memory capacity see table 1.4 to 1.7 product list peripheral function port input/output : 87 pins, input : 1 pin multifunction timer timer a : 16 bits x 5 channels, timer b : 16 bits x 6 channels, three phase motor control circuit serial interface 3 channels clock synchronous, uart, i 2 c bus (1) , iebus (2) 2 channels clock synchronous a/d converter 10-bit a/d converter: 1 circuit, 26 channels d/a converter 8 bits x 2 channels dmac 2 channels crc calculation circuit ccitt-crc watchdog timer 15 bits x 1 channel (with prescaler) interrupt internal: 29 sources, external: 8 sources, software: 4 sources, priority level: 7 levels clock generation circuit 4 circuits main clock generation circuit (*), subclock generation circuit (*), on-chip oscillator, pll synthesizer (*)equipped with a built-in feedback resistor. oscillation stop detection function stop detection of main clock oscillation, re-oscillation detection function voltage detection circuit available (option (5) )absent electric characteristics supply voltage vcc1=3.0 to 5.5 v, vcc2=2.7v to vcc1 (f(bclk=24mhz) vcc1=2.7 to 5.5 v, vcc2=2.7v to vcc1 (f(bclk=10mhz) vcc1=vcc2=4.0 to 5.5v (f(bclk=24mhz) power consumption 14 ma (vcc1=vcc2=5v, f(bclk)=24mhz) 8 ma (vcc1=vcc2=3v, f(bclk)=10mhz) 1.8 a (vcc1=vcc2=3v, f(xcin)=32khz, wait mode) 0.7 a (vcc1=vcc2=3v, stop mode) 14 ma (vcc1=vcc2=5v, f(bclk)=24mhz) 2.0 a (vcc1=vcc2=5v, f(xcin)=32khz, wait mode) 0.8 a (vcc1=vcc2=5v, stop mode) flash memory version program/erase supply voltage 3.30.3 v or 5.00.5 v 5.00.5 v program and erase endurance 100 times (all area) or 1,000 times (user rom area without block a and block 1) / 10,000 times (block a, block 1) (3) operating ambient temperature -20 to 85 c, -40 to 85 c (3) t version : -40 to 85 c v version : -40 to 125 c package 100-pin plastic mold qfp, lqfp m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 4 of 96 rej03b0001-0241 notes: 1. i 2 c bus is a registered trademark of koninklijke philips electronics n. v. 2. iebus is a registered trademark of nec electronics corporation. 3. see table 1.8 and 1.9 product code for the program and erase end urance, and operating ambient temperature. in addition 1,000 times/10,000 times ar e under development as of jul., 2005. please inquire about a release schedule. 4. all options are on request basis. table 1.3 performance outline of m16c/62p group (m16c/62p, m16c/62pt)(80-pin version) item performance m16c/62p m16c/62pt (4) cpu number of basic instructions 91 instructions minimum instruction execution time 41.7ns(f(bclk)=24mhz, vcc1=3.3 to 5.5v) 100ns(f(bclk)=10mhz, vcc1=2.7 to 5.5v) 41.7ns(f(bclk)=24mhz, vcc1=4.0 to 5.5v) operating mode single-chip mode address space 1 mbyte memory capacity see table 1.4 to 1.7 product list peripheral function port input/output : 70 pins, input : 1 pin multifunction timer timer a : 16 bits x 5 channels (timer a1 and a2 are internal timer), timer b : 16 bits x 6 channels (timer b1 is internal timer) serial interface 2 channels clock synchronous, uart, i 2 c bus (1) , iebus (2) 1 channel clock synchronous, i 2 c bus (1) , iebus (2) 2 channels clock synchronous (1 channel is only transmission) a/d converter 10-bit a/d converter: 1 circuit, 26 channels d/a converter 8 bits x 2 channels dmac 2 channels crc calculation circuit ccitt-crc watchdog timer 15 bits x 1 channel (with prescaler) interrupt internal: 29 sources, external: 5 sources, software: 4 sources, priority level: 7 levels clock generation circuit 4 circuits main clock generation circuit (*), subclock generation circuit (*), on-chip oscillator, pll synthesizer (*)equipped with a built-in feedback resistor. oscillation stop detection function stop detection of main clock oscillation, re-oscillation detection function voltage detection circuit available (option (4) )absent electric characteristics supply voltage vcc1=3.0 to 5.5 v, (f(bclk=24mhz) vcc1=2.7 to 5.5 v, (f(bclk=10mhz) vcc1=4.0 to 5.5v, (f(bclk=24mhz) power consumption 14 ma (vcc1=5v, f(bclk)=24mhz) 8 ma (vcc1=3v, f(bclk)=10mhz) 1.8 a (vcc1=3v, f(xcin)=32khz, wait mode) 0.7 a (vcc1=3v, stop mode) 14 ma (vcc1=5v, f(bclk)=24mhz) 2.0 a (vcc1=5v, f(xcin)=32khz, wait mode) 0.8 a (vcc1=5v, stop mode) flash memory version program/erase supply voltage 3.3 0.3v or 5.0 0.5v 5.0 0.5v program and erase endurance 100 times (all area) or 1,000 times (user rom area without block a and block 1) / 10,000 times (block a, block 1) (3) operating ambient temperature -20 to 85 c, -40 to 85 c (3) t version : -40 to 85 c v version : -40 to 125 c package 80-pin plastic mold qfp m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 5 of 96 rej03b0001-0241 1.3 block diagram figure 1.1 is a m16c/62p group (m16c/62p, m16c /62pt) 128-pin and 100-pin version block diagram, figure 1.2 is a m16c/62p group (m16c/62p, m16c/62pt) 80-pin version block diagram. figure 1.1 m16c/62p group (m16c/62p, m16c/62p t) 128-pin and 100-pin version block diagram output (timer a): 5 input (timer b): 6 internal peripheral functions watchdog timer (15 bits) dmac (2 channels) d/a converter (8 bits x 2 channels) memory rom (1) ram (2) a/d converter (10 bits x 8 channels expandable up to 26 channels) uart or clock synchronous serial i/o (8 bits x 3 channels) system clock generation circuit xin-xout xcin-xcout pll frequency synthesizer on-chip oscillator m16c/60 series16-bit cpu core port p0 8 port p1 8 port p2 8 8 8 8 port p6 8 8 r0l r0h r1h r1l r2 r3 a0 a1 fb sb isp usp intb crc arithmetic circuit (ccitt ) (polynomial : x 16 +x 12 +x 5 +1) multiplier 7 8 8 port p10 port p9 port p8_5 port p8 port p7 notes : 1. rom size depends on microcomputer type. 2. ram size depends on microcomputer type. 3. ports p11 to p14 exist only in 128-pin version. 4. use m16c/62pt on vcc1= vcc2. port p5 port p4 port p3 clock synchronous serial i/o (8 bits x 2 channels) pc flg timer (16-bit) three-phase motor control circuit 8 8 8 2 port p11 port p12 port p14 port p13 (3) m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 6 of 96 rej03b0001-0241 figure 1.2 m16c/62p group (m16c/62p, m16c/62pt) 80-pin version block diagram timer (16-bit) output (timer a): 5 input (timer b): 6 internal peripheral functions watchdog timer (15 bits) dmac (2 channels) d/a converter (8 bits x 2 channels) a/d converter (10 bits x 8 channels expandable up to 26 channels) uart or clock synchronous serial i/o (2 channels) uart (1 channel) system clock generation circuit xin-xout xcin-xcout pll frequency synthesizer on-chip oscillator m16c/60 series16-bit cpu core port p0 8 port p2 8 port p3 8 port p4 4 port p5 8 port p6 8 crc arithmetic circuit (ccitt ) (polynomial : x 16 +x 12 +x 5 +1) memory 4 7 7 8 port p10 port p9 port p8 port p7 port p8_5 rom (1) ram (2) notes : 1. rom size depends on microcomputer type. 2. ram size depends on microcomputer type. 3. to use a uart2, set the crd bit in the u2c0 register to ?1? (cts/rts function disabled). 4. there is no external connections for port p1, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. set the direction bits in these ports to ?1? (output mode), and set the output data to ?0? (?l?) using the program. clock synchronous serial i/o (8 bits x 2 channels) r0l r0h r1h r1l r2 r3 sb flg usp isp intb pc multiplier a0 a1 fb (4) (4) (3) m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 7 of 96 rej03b0001-0241 1.4 product list table 1.4 to 1.7 list the product list, figure 1.3 shows the type no., memory size, and package, table 1.8 lists the product code of flash memory version and romless vers ion for m16c/62p, and table 1.9 lists the product code of flash memory version for m16c/62pt. figure 1.4 s hows the marking diagram of flash memory version and rom-less version for m16c/62p (top view), and fi gure 1.5 shows the marking diagram of flash memory version for m16c/62pt (top view) at the time of rom order. (d): under development notes: 1. the old package type numbers of each package type are as follows. plqp0128kb-a : 128p6q-a, prqp0100jb-a : 100p6s-a, plqp0100kb-a : 100p6q-a, prqp0080ja-a : 80p6s-a table 1.4 product list (1) (m16c/62p) as of dec. 2005 type no. rom capacity ram capacity package type (1) remarks m30622m6p-xxxfp 48 kbytes 4 kbytes prqp0100jb-a mask rom version m30622m6p-xxxgp plqp0100kb-a m30622m8p-xxxfp 64 kbytes 4 kbytes prqp0100jb-a m30622m8p-xxxgp plqp0100kb-a m30623m8p-xxxgp prqp0080ja-a m30622map-xxxfp 96 kbytes 5 kbytes prqp0100jb-a m30622map-xxxgp plqp0100kb-a m30623map-xxxgp p rqp0080ja-a m30620mcp-xxxfp 128 kbytes 10 kbytes prqp0100jb-a m30620mcp-xxxgp p lqp0100kb-a m30621mcp-xxxgp p rqp0080ja-a m30622mep-xxxfp 192 kbytes 12 kbytes prqp0100jb-a m30622mep-xxxgp plqp0100kb-a m30623mep-xxxgp plqp0128kb-a m30622mgp-xxxfp 256 kbytes 12 kbytes prqp0100jb-a m30622mgp-xxxgp plqp0100kb-a m30623mgp-xxxgp plqp0128kb-a m30624mgp-xxxfp 20 kbytes prqp0100jb-a m30624mgp-xxxgp plqp0100kb-a m30625mgp-xxxgp plqp0128kb-a m30622mwp-xxxfp 320 kbytes 16 kbytes prqp0100jb-a m30622mwp-xxxgp p lqp0100kb-a m30623mwp-xxxgp p lqp0128kb-a m30624mwp-xxxfp 24 kb ytes prqp0100jb-a m30624mwp-xxxgp p lqp0100kb-a m30625mwp-xxxgp p lqp0128kb-a m30626mwp-xxxfp 31 kb ytes prqp0100jb-a m30626mwp-xxxgp p lqp0100kb-a m30627mwp-xxxgp p lqp0128kb-a m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 8 of 96 rej03b0001-0241 (d): under development notes: 1. the old package type numbers of each package type are as follows. plqp0128kb-a : 128p6q-a, prqp0100jb-a : 100p6s-a, plqp0100kb-a : 100p6q-a, prqp0080ja-a : 80p6s-a 2. in the flash memory version, there is 4k bytes area (block a). 3. please use m3062lfgpfp and m3062lfgpgp for your new system instead of m30624fgpfp and m30624fgpgp. the m16c/62p group (m16c/62p, m1 6c/62pt) hardware manual is still good for m30624fgpfp and m30624fgpgp. table 1.5 product list (2) (m16c/62p) as of dec. 2005 type no. rom capacity ram capacity package type (1) remarks m30622mhp-xxxfp 384 kbytes 16 kbyt es prqp0100jb-a mask rom version m30622mhp-xxxgp plqp0100kb-a m30623mhp-xxxgp plqp0128kb-a m30624mhp-xxxfp 24 kbytes prqp0100jb-a m30624mhp-xxxgp plqp0100kb-a m30625mhp-xxxgp plqp0128kb-a m30626mhp-xxxfp 31 kbytes prqp0100jb-a m30626mhp-xxxgp plqp0100kb-a m30627mhp-xxxgp plqp0128kb-a m30626mjp-xxxfp (d) 512 kbytes 31 kbytes prqp0100jb-a m30626mjp-xxxgp ( d) plqp0100kb-a m30627mjp-xxxgp ( d) plqp0128kb-a m30622f8pfp 64k+4 kbytes 4 kbytes prqp0100jb-a flash memory version (2) m30622f8pgp plqp0100kb-a m30623f8pgp prqp0080ja-a m30620fcpfp 128k+4 kbytes 10 kbytes prqp0100jb-a m30620fcpgp plqp0100kb-a m30621fcpgp prqp0080ja-a m3062lfgpfp (3) (d) 256k+4 kbytes 20 kbytes prqp0100jb-a m3062lfgpgp (3) (d) plqp0100kb-a m30625fgpgp plqp0128kb-a m30626fhpfp 384k+4 kbytes 31 kbytes prqp0100jb-a m30626fhpgp plqp0100kb-a m30627fhpgp plqp0128kb-a m30626fjpfp 512k+4 kbytes 31 kbytes prqp0100jb-a m30626fjpgp plqp0100kb-a m30627fjpgp plqp0128kb-a m30622spfp ? 4 kbytes prqp0100jb-a rom-less version m30622spgp plqp0100kb-a m30620spfp 10 kbytes prqp0100jb-a m30620spgp plqp0100kb-a m30624spfp (d) ? 20 kbytes prqp0100jb-a m30624spgp (d) plqp0100kb-a m30626spfp (d) 31 kbytes prqp0100jb-a m30626spgp (d) plqp0100kb-a m30624fgpfp 256k+4 kbytes 20 kbytes prqp0100jb-a flash memory version m30624fgpgp plqp0100kb-a m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 9 of 96 rej03b0001-0241 (d): under development (p): under planning notes: 1. the old package type numbers of each package type are as follows. prqp0100jb-a : 100p6s-a, plqp0100kb-a : 100p6q-a, prqp0080ja-a : 80p6s-a 2. in the flash memory version, there is 4k bytes area (block a). table 1.6 product list (3) (t version (m16c/62pt)) as of dec. 2005 type no. rom capacity ram capacity package type (1) remarks m3062cm6t-xxxfp (d) 48 kbytes 4 kbytes prqp0100jb-a mask rom version t version (high reliability 85 c version) m3062cm6t-xxxgp (d) plqp0100kb-a m3062em6t-xxxgp (p) prqp0080ja-a m3062cm8t-xxxfp (d) 64 kbyt es 4 kbytes prqp0100jb-a m3062cm8t-xxxgp (d) plqp0100kb-a m3062em8t-xxxgp (p) prqp0080ja-a m3062cmat-xxxfp (d) 96 kbytes 5 kbytes prqp0100jb-a m3062cmat-xxxgp (d) plqp0100kb-a m3062emat-xxxgp (p) prqp0080ja-a m3062amct-xxxfp (d) 128 kbytes 10 kbytes prqp0100jb-a m3062amct-xxxgp (d) plqp0100kb-a m3062bmct-xxxgp (p) prqp0080ja-a m3062cf8tfp (d) 64 k+4 kbytes 4 kbytes prqp0100jb-a flash memory version (2) m3062cf8tgp plqp0100kb-a m3062afctfp (d) 128k+4 kbytes 10 kbytes prqp0100jb-a m3062afctgp (d) plqp0100kb-a m3062bfctgp (p) prqp0080ja-a m3062jfhtfp (d) 384k+4 kbytes 31 kbytes prqp0100jb-a m3062jfhtgp (d) plqp0100kb-a m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 10 of 96 rej03b0001-0241 (d): under development (p): under planning notes: 1. the old package type numbers of each package type are as follows. plqp0128kb-a : 128p6q-a, prqp0100jb-a : 100p6s-a, plqp0100kb-a : 100p6q-a, prqp0080ja-a : 80p6s-a 2. in the flash memory version, there is 4k bytes area (block a). table 1.7 product list (4) (v version (m16c/62pt)) as of dec. 2005 type no. rom capacity ram capacity package type (1) remarks m3062cm6v-xxxfp (p) 48 kbytes 4 kbytes prqp0100jb-a mask rom version v version (high reliability 125 c version) m3062cm6v-xxxgp ( p) plqp0100kb-a m3062em6v-xxxgp (p) prqp0080ja-a m3062cm8v-xxxfp (p) 64 kbyt es 4 kbytes prqp0100jb-a m3062cm8v-xxxgp ( p) plqp0100kb-a m3062em8v-xxxgp (p) prqp0080ja-a m3062cmav-xxxfp (p) 96 kbyt es 5 kbytes prqp0100jb-a m3062cmav-xxxgp (p) plqp0100kb-a m3062emav-xxxgp (p) prqp0080ja-a m3062amcv-xxxfp (d) 128 kbyt es 10 kbytes prqp0100jb-a m3062amcv-xxxgp (d) plqp0100kb-a m3062bmcv-xxxgp (p) prqp0080ja-a m3062afcvfp (d) 128k+4 kbytes 10 kbytes prqp0100jb-a flash memory version (2) m3062afcvgp (d) plqp0100kb-a m3062bfcvgp (p) prqp0080ja-a m3062jfhvfp (p) 384k+4 kbytes 31 kbytes prqp0100jb-a m3062jfhvgp (p) plqp0100kb-a m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 11 of 96 rej03b0001-0241 figure 1.3 type no., memory size, and package package type: fp : package prqp0100jb-a (100p6s-a) gp : package prqp0080ja-a (80p6s-a), plqp0100kb-a (100p6q-a), plqp0128kb-a (128p6q-a), rom no. omitted for flash memory version and romless version memory type: m: mask rom version f: flash memory version s: rom-less version type no. m 3 0 6 2 6 m h p - x x x f p m16c/62(p) group m16c family shows ram capacity, pin count, etc numeric, alphabet (l) : m16c/62p alphabet (l is excluded.) : m16c/62pt rom capacity: 6: 48 kbytes 8: 64 kbytes a: 96 kbytes c: 128 kbytes e: 192 kbytes g: 256 kbytes w: 320 kbytes h: 384 kbytes j: 512 kbytes classification p : m16c/62p t : t version (m16c/62pt) v : v version (m16c/62pt) m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 12 of 96 rej03b0001-0241 figure 1.4 marking diagram of flash memory version and rom-less version for m16c/62p (top view) table 1.8 product code of flash memory version and romless version for m16c/62p product code package internal rom (user rom area without block a, block 1) internal rom (block a, block 1) operating ambient temperature program and erase endurance temperature range program and erase endurance temperature range flash memory version d3 lead- included 100 0 c to 60 c 100 0 c to 60 c-40 c to 85 c d5 -20 c to 85 c d7 1,000 10,000 -40 c to 85 c-40 c to 85 c d9 -20 c to 85 c-20 c to 85 c u3 lead-free 100 100 0 c to 60 c-40 c to 85 c u5 -20 c to 85 c u7 1,000 10,000 -40 c to 85 c-40 c to 85 c u9 -20 c to 85 c-20 c to 85 c rom-less version d3 lead- included ?? ? ? -40 c to 85 c d5 -20 c to 85 c u3 lead-free ?? ? ? -40 c to 85 c u5 -20 c to 85 c m1 6 c m30626fhpfp bd5 xxxxxxx type no. (see figure 1.3 type no., memory size, and package ) chip version and product code b : shows chip version. henceforth, whenever it changes a version, it continues with b, c, and d. d5 : shows product code. (see table 1.8 product code ) date code seven digits the product without marking of chip version of the flash memory version and the romless version corresponds to the chip version ?a?. m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 13 of 96 rej03b0001-0241 figure 1.5 marking diagram of flash memory version for m16c/62pt (top view) table 1.9 product code of flash memory version for m16c/62pt product code package internal rom (user rom area without block a, block 1) internal rom (block a, block 1) operating ambient temperature program and erase endurance temperature range program and erase endurance temperature range flash memory version t version b lead- included 100 0 c to 60 c1000 c to 60 c-40 c to 85 c v version -40 c to 125 c t version b7 1,000 10,000 -40 c to 85 c-40 c to 85 c v version -40 c to 125 c-40 c to 125 c t version u lead-free 100 100 0 c to 60 c-40 c to 85 c v version -40 c to 125 c t version u7 1,000 10,000 -40 c to 85 c-40 c to 85 c v version -40 c to 125 c-40 c to 125 c m1 6 c m3 0 6 2 j f ht f p yyy xxxxxxx type no. (see figure 1.3 type no., memory size, and package ) date code seven digits notes: 1. : blank product code. (see table 1.9 product code ) ? ? : product code ?b? ? p b f ? : product code ?u? ? b 7 ? : product code ?b? ? u 7 ? : product code ?u7? m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 14 of 96 rej03b0001-0241 1.5 pin configuration figures 1.6 to 1.9 show the pin configuration (top view). figure 1.6 pin configuration (top view) 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 104 105 106 107 108 31 32 33 34 35 36 37 66 67 68 69 70 71 72 38 65 64 103 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p 1 _ 1 / d 9 p1_2/d10 avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p7_4/ta2out/w p7_6/ta3out p5_6/ale p7_7/ta3in p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd p5_7/rdy/clkout p4_7/cs3 p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/clk4 p9_6/anex1/sout4 p9_1/tb1in/sin3 p9_2/tb2in/sout3 p8_0/ta4out/u p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p8_2/int0 p8_3/int1 p8_5/nmi p4_5/cs1 p4_6/cs2 p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in/clk3 p7_2/clk2/ta1out/v p7_1/rxd2/scl2/ta0in/tb5in (1) p7_0/txd2/sda2/ta0out (1) p8_4/int2/zp p8_1/ta4in/u p7_3/cts2/rts2/ta1in/v p7_5/ta2in/w p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 vref avcc p9_7/adtrg/sin4 p14_1 p14_0 p13_7 p13_6 p13_5 p13_4 p1_3/d11 p1_4/d12 p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) p3_0/a8(/-/d7) p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 vcc2 vss p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p12_4 p12_3 p11_3 p11_2 p11_1 p11_0 vcc1 vss p13_0 p13_1 p13_2 p13_3 p12_5 p12_6 p12_7 p11_4 p11_5 p11_6 p11_7 p12_2 p12_1 p12_0 m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 15 of 96 rej03b0001-0241 table 1.10 pin characteristics for 128-pin package (1) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 1vref 2avcc 3 p9_7 sin4 adtrg 4 p9_6 sout4 anex1 5 p9_5 clk4 anex0 6p9_4 tb4in da1 7p9_3 tb3in da0 8 p9_2 tb2in sout3 9 p9_1 tb1in sin3 10 p9_0 tb0in clk3 11 p14_1 12 p14_0 13 byte 14 cnvss 15 xcin p8_7 16 xcout p8_6 17 reset 18 xout 19 vss 20 xin 21 vcc1 22 p8_5 nmi 23 p8_4 int2 zp 24 p8_3 int1 25 p8_2 int0 26 p8_1 ta4in/u 27 p8_0 ta4out/u 28 p7_7 ta3in 29 p7_6 ta3out 30 p7_5 ta2in/w 31 p7_4 ta2out/w 32 p7_3 ta1in/v cts2 /rts2 33 p7_2 ta1out/v clk2 34 p7_1 ta0in/tb5in rxd2/scl2 35 p7_0 ta0out txd2/sda2 36 p6_7 txd1/sda1 37 vcc1 38 p6_6 rxd1/scl1 39 vss 40 p6_5 clk1 41 p6_4 cts1 /rts1 /cts0 /clks1 42 p6_3 txd0/sda0 43 p6_2 rxd0/scl0 44 p6_1 clk0 45 p6_0 cts0 /rts0 46 p13_7 47 p13_6 48 p13_5 49 p13_4 50 p5_7 rdy /clkout m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 16 of 96 rej03b0001-0241 table 1.11 pin characteristics for 128-pin package (2) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 51 p5_6 ale 52 p5_5 hold 53 p5_4 hlda 54 p13_3 55 p13_2 56 p13_1 57 p13_0 58 p5_3 bclk 59 p5_2 rd 60 p5_1 wrh /bhe 61 p5_0 wrl /wr 62 p12_7 63 p12_6 64 p12_5 65 p4_7 cs3 66 p4_6 cs2 67 p4_5 cs1 68 p4_4 cs0 69 p4_3 a19 70 p4_2 a18 71 p4_1 a17 72 p4_0 a16 73 p3_7 a15 74 p3_6 a14 75 p3_5 a13 76 p3_4 a12 77 p3_3 a11 78 p3_2 a10 79 p3_1 a9 80 p12_4 81 p12_3 82 p12_2 83 p12_1 84 p12_0 85 vcc2 86 p3_0 a8(/-/d7) 87 vss 88 p2_7 an2_7 a7(/d7/d6) 89 p2_6 an2_6 a6(/d6/d5) 90 p2_5 an2_5 a5(/d5/d4) 91 p2_4 an2_4 a4(/d4/d3) 92 p2_3 an2_3 a3(/d3/d2) 93 p2_2 an2_2 a2(/d2/d1) 94 p2_1 an2_1 a1(/d1/d0) 95 p2_0 an2_0 a0(/d0/-) 96 p1_7 int5 d15 97 p1_6 int4 d14 98 p1_5 int3 d13 99 p1_4 d12 100 p1_3 d11 m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 17 of 96 rej03b0001-0241 table 1.12 pin characteristics for 128-pin package (3) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 101 p1_2 d10 102 p1_1 d9 103 p1_0 d8 104 p0_7 an0_7 d7 105 p0_6 an0_6 d6 106 p0_5 an0_5 d5 107 p0_4 an0_4 d4 108 p0_3 an0_3 d3 109 p0_2 an0_2 d2 110 p0_1 an0_1 d1 111 p0_0 an0_0 d0 112 p11_7 113 p11_6 114 p11_5 115 p11_4 116 p11_3 117 p11_2 118 p11_1 119 p11_0 120 p10_7 ki3 an7 121 p10_6 ki2 an6 122 p10_5 ki1 an5 123 p10_4 ki0 an4 124 p10_3 an3 125 p10_2 an2 126 p10_1 an1 127 avss 128 p10_0 an0 m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 18 of 96 rej03b0001-0241 figure 1.7 pin configuration (top view) 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p1_1/d9 p1_2/d10 p1_3/d11 p1_4/d12 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) p3_0/a8(/-/d7) p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 p7_4/ta2out/w p7_6/ta3out p5_6/ale p7_7/ta3in p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd vcc2 vss p5_7/rdy/clkout p4_5/cs1 p4_6/cs2 p4_7/cs3 avcc p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/clk4 p9_6/anex1/sout4 p9_1/tb1in/sin3 p9_2/tb2in/sout3 p8_0/ta4out/u p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p7_2/clk2/ta1out/v p8_2/int0 p7_1/rxd2/scl2/ta0in/tb5in (1) p8_3/int1 p8_5/nmi p9_7/adtrg/sin4 p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in/clk3 p7_0/txd2/sda2/ta0out (1) p8_4/int2/zp p8_1/ta4in/u p7_3/cts2/rts2/ta1in/v p7_5/ta2in/w p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 19 of 96 rej03b0001-0241 figure 1.8 pin configuration (top view) 12345678910111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p1_1/d9 p1_2/d10 p1_3/d11 p1_4/d12 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) p3_0/a8(/-/d7) p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 p7_4/ta2out/w p7_6/ta3out p5_6/ale p7_7/ta3in p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd vcc2 vss p5_7/rdy/clkout p4_5/cs1 p4_6/cs2 p4_7/cs3 avcc p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/clk4 p9_6/anex1/sout4 p9_1/tb1in/sin3 p9_2/tb2in/sout3 p8_0/ta4out/u p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p8_2/int0 p8_3/int1 p8_5/nmi p9_7/adtrg/sin4 p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in/clk3 p8_4/int2/zp p7_2/clk2/ta1out/v p7_1/rxd2/scl2/ta0in/tb5in (1) p7_0/txd2/sda2/ta0out (1) p7_5/ta2in/w p7_3/cts2/rts2/ta1in/v p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p8_1/ta4in/u m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 20 of 96 rej03b0001-0241 table 1.13 pin characteristics for 100-pin package (1) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin fp gp 1 99 p9_6 sout4 anex1 2 100 p9_5 clk4 anex0 31 p9_4 tb4in da1 4 2 p9_3 tb3in da0 5 3 p9_2 tb2in sout3 6 4 p9_1 tb1in sin3 7 5 p9_0 tb0in clk3 86byte 9 7 cnvss 10 8 xcin p8_7 11 9 xcout p8_6 12 10 reset 13 11 xout 14 12 vss 15 13 xin 16 14 vcc1 17 15 p8_5 nmi 18 16 p8_4 int2 zp 19 17 p8_3 int1 20 18 p8_2 int0 21 19 p8_1 ta4in/u 22 20 p8_0 ta4out/u 23 21 p7_7 ta3in 24 22 p7_6 ta3out 25 23 p7_5 ta2in/w 26 24 p7_4 ta2out/w 27 25 p7_3 ta1in/v cts2 /rts2 28 26 p7_2 ta1out/v clk2 29 27 p7_1 ta0in/tb5in rxd2/scl2 30 28 p7_0 ta0out txd2/sda2 31 29 p6_7 txd1/sda1 32 30 p6_6 rxd1/scl1 33 31 p6_5 clk1 34 32 p6_4 cts1 /rts1 /cts0 /clks1 35 33 p6_3 txd0/sda0 36 34 p6_2 rxd0/scl0 37 35 p6_1 clk0 38 36 p6_0 cts0 /rts0 39 37 p5_7 rdy /clkout 40 38 p5_6 ale 41 39 p5_5 hold 42 40 p5_4 hlad 43 41 p5_3 bclk 44 42 p5_2 rd 45 43 p5_1 wrh /bhe 46 44 p5_0 wrl /wr 47 45 p4_7 cs3 48 46 p4_6 cs2 49 47 p4_5 cs1 50 48 p4_4 cs0 m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 21 of 96 rej03b0001-0241 table 1.14 pin characteristics for 100-pin package (2) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin fp gp 51 49 p4_3 a19 52 50 p4_2 a18 53 51 p4_1 a17 54 52 p4_0 a16 55 53 p3_7 a15 56 54 p3_6 a14 57 55 p3_5 a13 58 56 p3_4 a12 59 57 p3_3 a11 60 58 p3_2 a10 61 59 p3_1 a9 62 60 vcc2 63 61 p3_0 a8(/-/d7) 64 62 vss 65 63 p2_7 an2_7 a7(/d7/d6) 66 64 p2_6 an2_6 a6(/d6/d5) 67 65 p2_5 an2_5 a5(/d5/d4) 68 66 p2_4 an2_4 a4(/d4/d3) 69 67 p2_3 an2_3 a3(/d3/d2) 70 68 p2_2 an2_2 a2(/d2/d1) 71 69 p2_1 an2_1 a1(/d1/d0) 72 70 p2_0 an2_0 a0(/d0/-) 73 71 p1_7 int5 d15 74 72 p1_6 int4 d14 75 73 p1_5 int3 d13 76 74 p1_4 d12 77 75 p1_3 d11 78 76 p1_2 d10 79 77 p1_1 d9 80 78 p1_0 d8 81 79 p0_7 an0_7 d7 82 80 p0_6 an0_6 d6 83 81 p0_5 an0_5 d5 84 82 p0_4 an0_4 d4 85 83 p0_3 an0_3 d3 86 84 p0_2 an0_2 d2 87 85 p0_1 an0_1 d1 88 86 p0_0 an0_0 d0 89 87 p10_7 ki3 an7 90 88 p10_6 ki2 an6 91 89 p10_5 ki1 an5 92 90 p10_4 ki0 an4 93 91 p10_3 an3 94 92 p10_2 an2 95 93 p10_1 an1 96 94 avss 97 95 p10_0 an0 98 96 vref 99 97 avcc 100 98 p9_7 sin4 adtrg m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 22 of 96 rej03b0001-0241 figure 1.9 pin configuration (top view) 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 56 p4_2 p3_0 p3_1 p3_2 p3_3 p3_4 p3_5 p3_6 p3_7 p4_0 p4_1 p0_0/an0_0 p0_1/an0_1 p0_2/an0_2 p0_3/an0_3 p0_4/an0_4 p0_5/an0_5 p0_6/an0_6 p0_7/an0_7 p10_1/an1 p10_2/an2 p10_3/an3 p10_4/an4/ki0 p10_5/an5/ki1 p10_6/an6/ki2 p10_7/an7/ki3 p2_0/an2_0 p2_1/an2_1 p2_2/an2_2 p2_4/an2_4 p2_5/an2_5 p2_6/an2_6 p2_7/an2_7 p2_3/an2_3 m16c/62p group (m16c/62p, m16c/62pt) package : prqp0080ja-a (80p6s-a) notes: 1. p7_0 and p7_1 are n channel open-drain output pins. pin configuration (top view) 1 2 3 4 5 6 7 8 9 1011121314151617 75 76 77 78 79 80 vcc1 xin xout vss reset cnvss(byte) p8_7/xcin p8_6/xcout p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/clk4 p8_2/int0 p8_3/int1 p8_1/ta4in p8_4/int2/zp p8_0/ta4out p8_5/nmi vref avss avcc p10_0/an0 p9_6/anex1/sout4 p9_0/tb0in/clk3 p9_7/adtrg/sin4 p9_2/tb2in/sout3 18 19 20 21 22 23 24 25 26 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p7_1/rxd2/scl2/ta0in/tb5in (1) p7_0/txd2/sda2/ta0out (1) p7_6/ta3out p7_7/ta3in 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 p4_3 p5_6 p5_5 p5_4 p5_3 p5_2 p5_7/clkout p6_3/txd0/sda0 p6_1/clk0 p6_2/rxd0/scl0 p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p5_0 p5_1 m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 23 of 96 rej03b0001-0241 table 1.15 pin characteristics for 80-pin package (1) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 1 p9_5 clk4 anex0 2p9_4 tb4in da1 3 p9_3 tb3in da0 4 p9_2 tb2in sout3 5 p9_0 tb0in clk3 6 cnvss (byte) 7xcin p8_7 8xcoutp8_6 9 reset 10 xout 11 vss 12 xin 13 vcc1 14 p8_5 nmi 15 p8_4 int2 zp 16 p8_3 int1 17 p8_2 int0 18 p8_1 ta4in 19 p8_0 ta4out 20 p7_7 ta3in 21 p7_6 ta3out 22 p7_1 ta0in/tb5in rxd2/scl2 23 p7_0 ta0out txd2/sda2 24 p6_7 txd1/sda1 25 p6_6 rxd1/scl1 26 p6_5 clk1 27 p6_4 cts1 /rts1 /cts0 /clks1 28 p6_3 txd0/sda0 29 p6_2 rxd0/scl0 30 p6_1 clk0 31 p6_0 cts0 /rts0 32 p5_7 clkout 33 p5_6 34 p5_5 35 p5_4 36 p5_3 37 p5_2 38 p5_1 39 p5_0 40 p4_3 41 p4_2 42 p4_1 43 p4_0 44 p3_7 45 p3_6 46 p3_5 47 p3_4 48 p3_3 49 p3_2 50 p3_1 m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 24 of 96 rej03b0001-0241 table 1.16 pin characteristics for 80-pin package (2) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 51 p3_0 52 p2_7 an2_7 53 p2_6 an2_6 54 p2_5 an2_5 55 p2_4 an2_4 56 p2_3 an2_3 57 p2_2 an2_2 58 p2_1 an2_1 59 p2_0 an2_0 60 p0_7 an0_7 61 p0_6 an0_6 62 p0_5 an0_5 63 p0_4 an0_4 64 p0_3 an0_3 65 p0_2 an0_2 66 p0_1 an0_1 67 p0_0 an0_0 68 p10_7 ki3 an7 69 p10_6 ki2 an6 70 p10_5 ki1 an5 71 p10_4 ki0 an4 72 p10_3 an3 73 p10_2 an2 74 p10_1 an1 75 avss 76 p10_0 an0 77 vref 78 avcc 79 p9_7 sin4 adtrg 80 p9_6 sout4 anex1 m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 25 of 96 rej03b0001-0241 1.6 pin description i : input o : output i/o : input and output power supply : power supplies which relate to the extern al bus pins are separated as vcc2, thus they can be interfaced using the different voltage as vcc1. notes: 1. in this manual, hereafter, vcc refers to vcc1 unless otherwise noted. 2. in m16c/62pt, apply 4.0 to 5.5 v to the vcc1 and vcc2 pins. also the apply condition is that vcc1 = vcc2. 3. when use vcc1 > vcc2, contacts due to some points or restrictions to be checked. 4. bus control pins in m16c/62pt cannot be used. table 1.17 pin description (100-pin and 128-pin version) (1) signal name pin name i/o type power supply (3) description power supply input vcc1,vcc2 vss i ? apply 2.7 to 5.5 v to the vcc1 and vcc2 pins and 0 v to the vss pin. the vcc apply condition is that vcc1 vcc2. (1, 2) analog power supply input avcc avss i vcc1 applies the power supply for the a/d converter. connect the avcc pin to vcc1. connect the avss pin to vss. reset input reset ivcc1 the microcomputer is in a reset st ate when applying ?l? to the this pin. cnvss cnvss i vcc1 switches processor mode. c onnect this pin to vss to when after a reset to start up in single-chip mode. connect this pin to vcc1 to start up in microprocessor mode. external data bus width select input byte i vcc1 switches the data bus in exter nal memory space. the data bus is 16 bits long when the this pin is held "l" and 8 bits long when the this pin is held "h". set it to either one. connect this pin to vss when an single-chip mode. bus control pins (4) d0 to d7 i/o vcc2 inputs and outputs data (d0 to d7) when these pins are set as the separate bus. d8 to d15 i/o vcc2 inputs and outputs data (d8 to d15) when external 16-bit data bus is set as the separate bus. a0 to a19 o vcc2 output address bits (a0 to a19). a0/d0 to a7/d7 i/o vcc2 input and output data (d0 to d7) and output address bits (a0 to a7) by timesharing when external 8-bit data bus are set as the multiplexed bus. a1/d0 to a8/d7 i/o vcc2 input and output data (d0 to d7 ) and output address bits (a1 to a8) by timesharing when external 16-bit data bus are set as the multiplexed bus. cs0 to cs3 o vcc2 output cs0 to cs3 signals. cs0 to cs3 are chip-select signals to specify an external space. wrl /wr wrh /bhe rd o vcc2 output wrl , wrh , (wr , bhe ), rd signals. wrl and wrh or bhe and wr can be switched by program. ? wrl , wrh and rd are selected the wrl signal becomes "l" by writing data to an even address in an external memory space. the wrh signal becomes "l" by writing data to an odd address in an external memory space. the rd pin signal becomes "l" by reading data in an external memory space. ? wr , bhe and rd are selected the wr signal becomes "l" by writing data in an external memory space. the rd signal becomes "l" by reading dat a in an external memory space. the bhe signal becomes "l" by accessing an odd address. select wr , bhe and rd for an external 8-bit data bus. ale o vcc2 ale is a signal to latch the address. hold i vcc2 while the hold pin is held "l", the microcomputer is placed in a hold state. hlda o vcc2 in a hold state, hlda outputs a "l" signal. rdy i vcc2 while applying a "l" signal to the rdy pin, the microcomputer is placed in a wait state. m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 26 of 96 rej03b0001-0241 i : input o : output i/o : input and output notes: 1. when use vcc1 > vcc2, contacts due to some points or restrictions to be checked. 2. this pin function in m16c/62pt cannot be used. 3. ask the oscillator maker the oscillation characteristic. table 1.18 pin description (100-pin and 128-pin version) (2) signal name pin name i/o type power supply (1) description main clock input xin i vcc1 i/o pins for the main clock generation circuit. connect a ceramic resonator or crystal oscillator between xin and xout (3) . to use the external clock, input the clock from xin and leave xout open. main clock output xout o vcc1 sub clock input xcin i vcc1 i/o pins for a sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout (3) . to use the external clock, input the clock from xcin and leave xcout open. sub clock output xcout o vcc1 bclk output (2) bclk o vcc2 outputs the bclk signal. clock output clkout o vcc2 the clock of the same cycle as fc, f8, or f32 is outputted. int interrupt input int0 to int2 i vcc1 input pins for the int interrupt. nt3 to int5 i vcc2 nmi interrupt input nmi i vcc1 input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register. key input interrupt input ki0 to ki3 i vcc1 input pins for the key input interrupt. timer a ta0out to ta4out i/o vcc1 these are timer a0 to timer a4 i/o pins. (however, output of ta0out for the n-channel open drain output.) ta0in to ta4in i vcc1 these are timer a0 to timer a4 input pins. zp i vcc1 input pin for the z-phase. timer b tb0in to tb5in i vcc1 these are timer b0 to timer b5 input pins. three-phase motor control output u, u , v, v , w, w o vcc1 these are three-phase motor control output pins. serial interface cts0 to cts2 i vcc1 these are send control input pins. rts0 to rts2 o vcc1 these are receive control output pins. clk0 to clk4 i/o vcc1 these are transfer clock i/o pins. rxd0 to rxd2 i vcc1 these are serial data input pins. sin3, sin4 i vcc1 these are serial data input pins. txd0 to txd2 o vcc1 these are serial data output pins . (however, output of txd2 for the n-channel open drain output.) sout3, sout4 o vcc1 these are serial data output pins. clks1 o vcc1 this is output pin for trans fer clock output from multiple pins function. i 2 c mode sda0 to sda2 i/o vcc1 these are serial data i/o pins. (however, output of sda2 for the n- channel open drain output.) scl0 to scl2 i/o vcc1 these are transfer clock i/o pins. (however, output of scl2 for the n-channel open drain output.) m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 27 of 96 rej03b0001-0241 i : input o : output i/o : input and output notes: 1. when use vcc1 > vcc2, contacts due to some points or restrictions to be checked. 2. ports p11 to p14 in m16c/62p (100-pin version) and m16c/62pt (100-pin version) cannot be used. table 1.19 pin description (100-pin and 128-pin version) (3) signal name pin name i/o type power supply (1) description reference voltage input vref i vcc1 applies the reference voltage for the a/d converter and d/a converter. a/d converter an0 to an7, an0_0 to an0_7, an2_0 to an2_7 i vcc1 analog input pins for the a/d converter. adtrg i vcc1 this is an a/d trigger input pin. anex0 i/o vcc1 this is the extended analog in put pin for the a/d converter, and is the output in external op-amp connection mode. anex1 i vcc1 this is the extended analog input pin for the a/d converter. d/a converter da0, da1 o vcc1 this is the output pin for the d/a converter. i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7 (2) , p13_0 to p13_7 (2) i/o vcc2 8-bit i/o ports in cmos, having a direction register to select an input or output. each pin is set as an input port or output port. an input port can be set for a pull-up or for no pull-up in 4-bit unit by program. p6_0 to p6_7, p7_0 to p7_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7 (2) i/o vcc1 8-bit i/o ports having equivalent functions to p0. (however, output of p7_0 and p7_1 for the n-channel open drain output.) p8_0 to p8_4, p8_6, p8_7, p14_0, p14_1 (2) i/o vcc1 i/o ports having equivalent functions to p0. input port p8_5 i vcc1 input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register. m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 28 of 96 rej03b0001-0241 i : input o : output i/o : input and output notes: 1. in this manual, hereafter, vcc refers to vcc1 unless otherwise noted. 2. in m16c/62pt, apply 4.0 to 5.5 v to the vcc1 pin. 3. ask the oscillator maker the oscillation characteristic. table 1.20 pin description (80-pin version) (1) (1) signal name pin name i/o type power supply description power supply input vcc1, vss i ? apply 2.7 to 5.5 v to the vcc1 pin and 0 v to the vss pin. (1, 2) analog power supply input avcc avss i vcc1 applies the power supply for the a/d converter. connect the avcc pin to vcc1. co nnect the avss pin to vss. reset input reset ivcc1 the microcomputer is in a reset st ate when applying ?l? to the this pin. cnvss cnvss (byte) ivcc1 switches processor mode. connect this pin to vss to when after a reset to start up in single-chip mode. connect this pin to vcc1 to start up in microprocessor mode. as for the byte pin of the 80-pin versions, pull-up processing is perf ormed within the microcomputer. main clock input xin i vcc1 i/o pins for the main clock generation circuit. connect a ceramic resonator or crystal oscillator between xin and xout (3) . to use the external clock, input the clock from xin and leave xout open. main clock output xout o vcc1 sub clock input xcin i vcc1 i/o pins for a sub cl ock oscillation circuit. connect a crystal oscillator between xcin and xcout (3) . to use the external clock, input the clock from xcin and leave xcout open. sub clock output xcout o vcc1 clock output clkout o vcc2 the clock of the same cycle as fc, f8, or f32 is outputted. int interrupt input int0 to int2 i vcc1 input pins for the int interrupt. nmi interrupt input nmi i vcc1 input pin for the nmi interrupt. key input interrupt input ki0 to ki3 i vcc1 input pins for the key input interrupt. timer a ta0out, ta3out, ta4out i/o vcc1 these are timer a0,timer a3 and timer a4 i/o pins. (however, output of ta0out for the n- channel open drain output.) ta0in, ta3in, ta4in i vcc1 these are timer a0, timer a3 and timer a4 input pins. zp i vcc1 input pin for the z-phase. timer b tb0in, tb2in to tb5in i vcc1 these are timer b0, timer b2 to timer b5 input pins. serial interface cts0 to cts1 i vcc1 these are send control input pins. rts0 to rts1 o vcc1 these are receive control output pins. clk0, clk1, clk3, clk4 i/o vcc1 these are transfer clock i/o pins. rxd0 to rxd2 i vcc1 these are serial data input pins. sin4 i vcc1 this is serial data input pin. txd0 to txd2 o vcc1 these are serial data output pins. (however, output of txd2 for the n-channel open drain output.) sout3, sout4 o vcc1 these are serial data output pins. clks1 o vcc1 this is output pin for transfe r clock output from multiple pins function. i 2 c mode sda0 to sda2 i/o vcc1 these are serial data i/o pins. (however, output of sda2 for the n-channel open drain output.) scl0 to scl2 i/o vcc1 these are transfer clock i/o pins. (however, output of scl2 for the n-channel open drain output.) m16c/62p group (m16c/62p, m16c/62pt) 1. overview rev.2.41 jan 10, 2006 page 29 of 96 rej03b0001-0241 i : input o : output i/o : input and output notes: 1. there is no external connections for port p1, p4_4 to p 4_7, p7_2 to p7_5 and p9_1 in 80-pin version. set the direction bits in these ports to ?1? (output mode), a nd set the output data to ?0? (?l?) using the program. table 1.21 pin description (80-pin version) (2) signal name pin name i/o type power supply (1) description reference voltage input vref i vcc1 applies the reference voltage for the a/d converter and d/a converter. a/d converter an0 to an7, an0_0 to an0_7, an2_0 to an2_7 i vcc1 analog input pins for the a/d converter. adtrg i vcc1 this is an a/d trigger input pin. anex0 i/o vcc1 this is the extended analog in put pin for the a/d converter, and is the output in external op-amp connection mode. anex1 i vcc1 this is the extended analog input pin for the a/d converter. d/a converter da0, da1 o vcc1 this is the output pin for the d/a converter. i/o port (1) p0_0 to p0_7, p2_0 to p2_7, p3_0 to p3_7, p5_0 to p5_7, p6_0 to p6_7, p10_0 to p10_7 i/o vcc1 8-bit i/o ports in cmos, having a direction register to select an input or output. each pin is set as an input port or output port. an input port can be set for a pull-up or for no pull-up in 4-bit unit by program. p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7 i/o vcc1 i/o ports having equivalent functions to p0. p4_0 to p4_3, p7_0, p7_1, p7_6, p7_7 i/o vcc1 i/o ports having equivalent functions to p0. (however, output of p7_0 and p7_1 for the n-channel open drain output.) input port p8_5 i vcc1 input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register. m16c/62p group (m16c/62p, m16c/62pt) 2. central processing unit (cpu) rev.2.41 jan 10, 2006 page 30 of 96 rej03b0001-0241 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 2.1 central processing unit register 2.1 data registers (r 0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32-bit data register (r2r0). r3r1 is the same as r2r0. data registers (1) address registers (1) frame base registers (1) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register notes: 1. these registers comprise a register bank. there are two register banks. r0h b15 b8 b7 b0 r3 intbh usp isp sb c d z s b o i u ipl r0l r1h r1l r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt en able flag stack pointer select flag reserved area processor interrupt priority level m16c/62p group (m16c/62p, m16c/62pt) 2. central processing unit (cpu) rev.2.41 jan 10, 2006 page 31 of 96 rej03b0001-0241 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, an d is used for address regist er indirect addressing an d address register relative addressing. they also are used for transfers and logic/logic opera tions. a1 is the same as a0. in some instructions, registers a1 and a0 can be co mbined for use as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating th e start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured wi th 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out b it that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to ?0?. 2.8.3 zero flag (z flag) this flag is set to ?1? when an arithmetic operation resulted in 0; otherwise, it is ?0?. 2.8.4 sign flag (s flag) this flag is set to ?1? when an arithmetic operation resulted in a nega tive value; otherwise, it is ?0?. 2.8.5 register bank se lect flag (b flag) register bank 0 is selected when this flag is ?0? ; register bank 1 is selected when this flag is ?1?. 2.8.6 overflow flag (o flag) this flag is set to ?1? when the operation resulted in an overflow; otherwise, it is ?0?. 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabl ed when the i flag is ?0?, and are enab led when the i flag is ?1?. the i flag is cleared to ?0? when the interrupt request is accepted. m16c/62p group (m16c/62p, m16c/62pt) 2. central processing unit (cpu) rev.2.41 jan 10, 2006 page 32 of 96 rej03b0001-0241 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is ?0?; usp is selected when the u flag is ?1?. the u flag is cleared to ?0? when a hardware interrupt request is accepte d or an int instru ction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor in terrupt priority le vels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write ?0?. when read, its content is indeterminate. m16c/62p group (m16c/62p , m16c/62pt) 3. memory rev.2.41 jan 10, 2006 page 33 of 96 rej03b0001-0241 3. memory figure 3.1 is a memory map of the m16c/62p group. th e address space extends the 1m bytes from address 00000h to fffffh. the internal rom is allocated in a lo wer address direction beginning with address fffffh. for example, a 64-kbyte internal rom is allocated to the addresses from f0000h to fffffh. as for the flash memory version, 4-kbyte space (block a) exists in 0f000h to 0ffffh. 4-kbyte space is mainly for storing data. in addition to storing da ta, 4-kbyte space also can store programs. the fixed interrupt vector table is allocated to the addres ses from fffdch to fffffh. therefore, store the start address of each inte rrupt routine here. the internal ram is allocated in an upper address direction beginning with address 00400h. for example, a 10-kbyte internal ram is allocated to the addresses from 00400h to 02bffh. in addition to storing data, the internal ram also stores the stack used when calling subroutines and when interrupts are generated. the srf is allocated to th e addresses from 00000h to 003ffh. peripheral f unction control registers are located here. of the sfr, any area which has no func tions allocated is reserved for futu re use and cannot be used by users. the special page vector table is allocat ed to the addresses from ffe00h to ff fdbh. this vector is used by the jmps or jsrs instruction. for details, refer to the m16c/60 and m16c/20 series software manual . in memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. use m16c/62p (80-pin version) and m16c/62pt in single -chip mode. the memory expansion and microprocessor modes cannot be used . figure 3.1 memory map 00000h xxxxxh external area internal rom (program area) (5) sfr internal ram reserved area (1) reserved area (2) fffdch notes: 1. during memory expansion and microprocessor modes, can be used. 2. in memory expansion mode, can be used. 3. as for the flash memory version, 4-kbyte space (block a) exists. 4. shown here is a memory map for the case where the pm10 bit in the pm1 register is ?1? and the pm13 bit in the pm1 register is ?1?. 5. when using the masked rom version, write nothing to internal rom area. undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc nmi 4 kbytes 013ffh 02bffh 017ffh address xxxxxh 033ffh 10 kbytes 5 kbytes 12 kbytes size address yyyyyh size f0000h e8000h f4000h 96 kbytes 48 kbytes 64 kbytes reserved area external area 00400h 10000h 27000h 28000h 80000h yyyyyh fffffh e0000h 256 kbytes 128 kbytes 192 kbytes d0000h 320 kbytes c0000h 384 kbytes b0000h a0000h 512 kbytes 80000h 063ffh 053ffh 07fffh 24 kbytes 20 kbytes 31 kbytes internal ram internal rom (3) 043ffh 16 kbytes ffe00h fffffh internal rom (data area) (3) 0ffffh 0f000h m16c/62p group (m16c/62p, m16c/62pt) 4. special function register (sfr) rev.2.41 jan 10, 2006 page 34 of 96 rej03b0001-0241 4. special function register (sfr) sfr(special function register) is the c ontrol register of peripheral functions. tables 4.1 to 4.6 list the sfr information. notes: 1. the blank areas are reserved and cannot be accessed by users. 2. the pm00 and pm01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. 3. the cm20, cm21, and cm27 bits do not change at oscillation stop detection reset. 4. the wdc5 bit is ?0? (cold start) immediately after power-on. i t can only be set to ?1? in a program. 5. this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. 6. this register in m16c/62pt cannot be used. x : nothing is mapped to this bit table 4.1 sfr information (1) (1) address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 (2) pm0 00000000b(cnvss pin is ?l?) 00000011b(cnvss pin is ?h?) 0005h processor mode register 1 pm1 00001000b 0006h system clock control register 0 cm0 01001000b 0007h system clock control register 1 cm1 00100000b 0008h chip select control register (6) csr 00000001b 0009h address match interrupt enable register aier xxxxxx00b 000ah protect register prcr xx000000b 000bh data bank register (6) dbr 00h 000ch oscillation stop detection register (3) cm2 0x000000b 000dh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00xxxxxxb (4) 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h x0h 0013h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h x0h 0017h 0018h 0019h voltage detection register 1 (5, 6) vcr1 00001000b 001ah voltage detection register 2 (5, 6) vcr2 00h 001bh chip select expansion control register (6) cse 00h 001ch pll control register 0 plc0 0001x010b 001dh 001eh processor mode register 2 pm2 xxx00000b 001fh low voltage detection interrupt register (6) d4int 00h 0020h dma0 source pointer sar0 xxh 0021h xxh 0022h xxh 0023h 0024h dma0 destination pointer dar0 xxh 0025h xxh 0026h xxh 0027h 0028h dma0 transfer counter tcr0 xxh 0029h xxh 002ah 002bh 002ch dma0 control register dm0con 00000x00b 002dh 002eh 002fh 0030h dma1 source pointer sar1 xxh 0031h xxh 0032h xxh 0033h 0034h dma1 destination pointer dar1 xxh 0035h xxh 0036h xxh 0037h 0038h dma1 transfer counter tcr1 xxh 0039h xxh 003ah 003bh 003ch dma1 control register dm1con 00000x00b 003dh 003eh 003fh m16c/62p group (m16c/62p, m16c/62pt) 4. special function register (sfr) rev.2.41 jan 10, 2006 page 35 of 96 rej03b0001-0241 notes: 1. the blank areas are reserved an d cannot be accessed by users. x : nothing is mapped to this bit table 4.2 sfr information (2) (1) address register symbol after reset 0040h 0041h 0042h 0043h 0044h int3 interrupt control register int3ic xx00x000b 0045h timer b5 interrupt control register tb5ic xxxxx000b 0046h timer b4 interrupt control register, uart1 bu s collision detection interrupt control register tb4ic, u1bcnic xxxxx000b 0047h timer b3 interrupt control register, uart0 bu s collision detection interrupt control register tb3ic, u0bcnic xxxxx000b 0048h si/o4 interrupt control register, int5 interrupt control register s4ic, int5ic xx00x000b 0049h si/o3 interrupt control register, int4 interrupt control register s3ic, int4ic xx00x000b 004ah uart2 bus collision detection interrupt control register bcnic xxxxx000b 004bh dma0 interrupt control register dm0ic xxxxx000b 004ch dma1 interrupt control register dm1ic xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh uart2 transmit interrupt control register s2tic xxxxx000b 0050h uart2 receive interrupt control register s2ric xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h timer a0 interrupt control register ta0ic xxxxx000b 0056h timer a1 interrupt control register ta1ic xxxxx000b 0057h timer a2 interrupt control register ta2ic xxxxx000b 0058h timer a3 interrupt control register ta3ic xxxxx000b 0059h timer a4 interrupt control register ta4ic xxxxx000b 005ah timer b0 interrupt control register tb0ic xxxxx000b 005bh timer b1 interrupt control register tb1ic xxxxx000b 005ch timer b2 interrupt control register tb2ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh int1 interrupt control register int1ic xx00x000b 005fh int2 interrupt control register int2ic xx00x000b 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh m16c/62p group (m16c/62p, m16c/62pt) 4. special function register (sfr) rev.2.41 jan 10, 2006 page 36 of 96 rej03b0001-0241 notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. this register is included in the flash memory version. x : nothing is mapped to this bit table 4.3 sfr information (3) (1) address register symbol after reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01afh 01b0h 01b1h 01b2h 01b3h 01b4h flash identification register (2) fidr xxxxxx00b 01b5h flash memory control register 1 (2) fmr1 0x00xx0xb 01b6h 01b7h flash memory control register 0 (2) fmr0 00000001b 01b8h address match interrupt register 2 rmad2 00h 01b9h 00h 01bah xxh 01bbh address match interrupt enable register 2 aier2 xxxxxx00b 01bch address match interrupt register 3 rmad3 00h 01bdh 00h 01beh xxh 01c0h to 024fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh peripheral clock select register pclkr 00000011b 025fh 0260h to 032fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033ah 033bh 033ch 033dh 033eh 033fh m16c/62p group (m16c/62p, m16c/62pt) 4. special function register (sfr) rev.2.41 jan 10, 2006 page 37 of 96 rej03b0001-0241 notes: 1. the blank areas are reserved an d cannot be accessed by users. x : nothing is mapped to this bit table 4.4 sfr information (4) (1) address register symbol after reset 0340h timer b3, 4, 5 count start flag tbsr 000xxxxxb 0341h 0342h timer a1-1 register ta11 xxh 0343h xxh 0344h timer a2-1 register ta21 xxh 0345h xxh 0346h timer a4-1 register ta41 xxh 0347h xxh 0348h three-phase pwm control register 0 invc0 00h 0349h three-phase pwm control register 1 invc1 00h 034ah three-phase output buffer register 0 idb0 00h 034bh three-phase output buffer register 1 idb1 00h 034ch dead time timer dtt xxh 034dh timer b2 interrupt occurrence frequency set counter ictb2 xxh 034eh 034fh 0350h timer b3 register tb3 xxh 0351h xxh 0352h timer b4 register tb4 xxh 0353h xxh 0354h timer b5 register tb5 xxh 0355h xxh 0356h 0357h 0358h 0359h 035ah 035bh timer b3 mode register tb3mr 00xx0000b 035ch timer b4 mode register tb4mr 00xx0000b 035dh timer b5 mode register tb5mr 00xx0000b 035eh interrupt factor select register 2 ifsr2a 00xxxxxxb 035fh interrupt factor select register ifsr 00h 0360h si/o3 transmit/receive register s3trr xxh 0361h 0362h si/o3 control register s3c 01000000b 0363h si/o3 bit rate generator s3brg xxh 0364h si/o4 transmit/receive register s4trr xxh 0365h 0366h si/o4 control register s4c 01000000b 0367h si/o4 bit rate generator s4brg xxh 0368h 0369h 036ah 036bh 036ch uart0 special mode register 4 u0smr4 00h 036dh uart0 special mode register 3 u0smr3 000x0x0xb 036eh uart0 special mode register 2 u0smr2 x0000000b 036fh uart0 special mode register u0smr x0000000b 0370h uart1 special mode register 4 u1smr4 00h 0371h uart1 special mode register 3 u1smr3 000x0x0xb 0372h uart1 special mode register 2 u1smr2 x0000000b 0373h uart1 special mode register u1smr x0000000b 0374h uart2 special mode register 4 u2smr4 00h 0375h uart2 special mode register 3 u2smr3 000x0x0xb 0376h uart2 special mode register 2 u2smr2 x0000000b 0377h uart2 special mode register u2smr x0000000b 0378h uart2 transmit/receive mode register u2mr 00h 0379h uart2 bit rate generator u2brg xxh 037ah uart2 transmit buffer register u2tb xxh 037bh xxh 037ch uart2 transmit/receive control register 0 u2c0 00001000b 037dh uart2 transmit/receive control register 1 u2c1 00000010b 037eh uart2 receive buffer register u2rb xxh 037fh xxh m16c/62p group (m16c/62p, m16c/62pt) 4. special function register (sfr) rev.2.41 jan 10, 2006 page 38 of 96 rej03b0001-0241 notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. bit 5 in the up-down flag is ?0? by reset. however, the values in these bits when read are indeterminate. x : nothing is mapped to this bit table 4.5 sfr information (5) (1) address register symbol after reset 0380h count start flag tabsr 00h 0381h clock prescaler reset fag cpsrf 0xxxxxxxb 0382h one-shot start flag onsf 00h 0383h trigger select register trgsr 00h 0384h up-down flag udf 00h (2) 0385h 0386h timer a0 register ta0 xxh 0387h xxh 0388h timer a1 register ta1 xxh 0389h xxh 038ah timer a2 register ta2 xxh 038bh xxh 038ch timer a3 register ta3 xxh 038dh xxh 038eh timer a4 register ta4 xxh 038fh xxh 0390h timer b0 register tb0 xxh 0391h xxh 0392h timer b1 register tb1 xxh 0393h xxh 0394h timer b2 register tb2 xxh 0395h xxh 0396h timer a0 mode register ta0mr 00h 0397h timer a1 mode register ta1mr 00h 0398h timer a2 mode register ta2mr 00h 0399h timer a3 mode register ta3mr 00h 039ah timer a4 mode register ta4mr 00h 039bh timer b0 mode register tb0mr 00xx0000b 039ch timer b1 mode register tb1mr 00xx0000b 039dh timer b2 mode register tb2mr 00xx0000b 039eh timer b2 special mode register tb2sc xxxxxx00b 039fh 03a0h uart0 transmit/receive mode register u0mr 00h 03a1h uart0 bit rate generator u0brg xxh 03a2h uart0 transmit buffer register u0tb xxh 03a3h xxh 03a4h uart0 transmit/receive control register 0 u0c0 00001000b 03a5h uart0 transmit/receive control register 1 u0c1 00xx0010b 03a6h uart0 receive buffer register u0rb xxh 03a7h xxh 03a8h uart1 transmit/receive mode register u1mr 00h 03a9h uart1 bit rate generator u1brg xxh 03aah uart1 transmit buffer register u1tb xxh 03abh xxh 03ach uart1 transmit/receive control register 0 u1c0 00001000b 03adh uart1 transmit/receive control register 1 u1c1 00xx0010b 03aeh uart1 receive buffer register u1rb xxh 03afh xxh 03b0h uart transmit/receive control register 2 ucon x0000000b 03b1h 03b2h 03b3h 03b4h 03b5h 03b6h 03b7h 03b8h dma0 request factor select register dm0sl 00h 03b9h 03bah dma1 request factor select register dm1sl 00h 03bbh 03bch crc data register crcd xxh 03bdh xxh 03beh crc input register crcin xxh 03bfh m16c/62p group (m16c/62p, m16c/62pt) 4. special function register (sfr) rev.2.41 jan 10, 2006 page 39 of 96 rej03b0001-0241 notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. at hardware reset 1 or hardware reset 2, the register is as follows: ? ?00000000b? where ?l? is inputted to the cnvss pin ? ?00000010b? where ?h? is inputted to the cnvss pin at software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: ? ?00000000b? where the pm01 to pm00 bits in the pm0 register are ?00b? (single-chip mode). ? ?00000010b? where the pm01 to pm00 bits in the pm0 register are ?01b? (memory expansion mode) or ?11b? (microprocessor mode) . 3. these registers do not exist in m16c/62p ( 80-pin version), and m16c/62pt (80-pin version). x : nothing is mapped to this bit table 4.6 sfr information (6) (1) address register symbol after reset 03c0h a/d register 0 ad0 xxh 03c1h xxh 03c2h a/d register 1 ad1 xxh 03c3h xxh 03c4h a/d register 2 ad2 xxh 03c5h xxh 03c6h a/d register 3 ad3 xxh 03c7h xxh 03c8h a/d register 4 ad4 xxh 03c9h xxh 03cah a/d register 5 ad5 xxh 03cbh xxh 03cch a/d register 6 ad6 xxh 03cdh xxh 03ceh a/d register 7 ad7 xxh 03cfh xxh 03d0h 03d1h 03d2h 03d3h 03d4h a/d control register 2 adcon2 00h 03d5h 03d6h a/d control register 0 adcon0 00000xxxb 03d7h a/d control register 1 adcon1 00h 03d8h d/a register 0 da0 00h 03d9h 03dah d/a register 1 da1 00h 03dbh 03dch d/a control register dacon 00h 03ddh 03deh port p14 control register (3) pc14 xx00xxxxb 03dfh pull-up control register 3 (3) pur3 00h 03e0h port p0 register p0 xxh 03e1h port p1 register p1 xxh 03e2h port p0 direction register pd0 00h 03e3h port p1 direction register pd1 00h 03e4h port p2 register p2 xxh 03e5h port p3 register p3 xxh 03e6h port p2 direction register pd2 00h 03e7h port p3 direction register pd3 00h 03e8h port p4 register p4 xxh 03e9h port p5 register p5 xxh 03eah port p4 direction register pd4 00h 03ebh port p5 direction register pd5 00h 03ech port p6 register p6 xxh 03edh port p7 register p7 xxh 03eeh port p6 direction register pd6 00h 03efh port p7 direction register pd7 00h 03f0h port p8 register p8 xxh 03f1h port p9 register p9 xxh 03f2h port p8 direction register pd8 00x00000b 03f3h port p9 direction register pd9 00h 03f4h port p10 register p10 xxh 03f5h port p11 register (3) p11 xxh 03f6h port p10 direction register pd10 00h 03f7h port p11 direction register (3) pd11 00h 03f8h port p12 register (3) p12 xxh 03f9h port p13 register (3) p13 xxh 03fah port p12 direction register (3) pd12 00h 03fbh port p13 direction register (3) pd13 00h 03fch pull-up control register 0 pur0 00h 03fdh pull-up control register 1 pur1 00000000b (2) 00000010b (2) 03feh pull-up control register 2 pur2 00h 03ffh port control register pcr 00h m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 40 of 96 rej03b0001-0241 5. electrical characteristics 5.1 electrical charac teristics (m16c/62p) notes: 1. there is no external connections for port p1_0 to p1_7, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc1 , v cc2 supply voltage v cc1 =av cc ? 0.3 to 6.5 v v cc2 supply voltage v cc2 ? 0.3 to v cc1 +0.1 v av cc analog supply voltage v cc1 =av cc ? 0.3 to 6.5 v v i input voltage reset , cnvss, byte, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1, vref, xin ? 0.3 to v cc1 +0.3 (1) v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 ? 0.3 to v cc2 +0.3 (1) v p7_0, p7_1 ? 0.3 to 6.5 v v o output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1, xout ? 0.3 to v cc1 +0.3 (1) v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 ? 0.3 to v cc2 +0.3 (1) v p7_0, p7_1 ? 0.3 to 6.5 v p d power dissipation ? 40 c m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 42 of 96 rej03b0001-0241 notes: 1. referenced to v cc1 = v cc2 = 2.7 to 5.5v at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified. 2. relationship between main clock os cillation frequency, and supply voltage. table 5.3 recommended operating conditions (2) (1) symbol parameter standard unit min. typ. max. f(xin) main clock input oscillation frequency (2) v cc1 =3.0v to 5.5v 016mhz v cc1 =2.7v to 3.0v 0 20v cc1 ? 44 mhz f(xcin) sub-clock oscillation frequency 32.768 50 khz f(ring) on-chip oscillation frequency 0.5 1 2 mhz f(pll) pll clock os cillation frequency (2) v cc1 =3.0v to 5.5v 10 24 mhz v cc1 =2.7v to 3.0v 10 46.67v cc1 ? 116 mhz f(bclk) cpu operation clock 0 24 mhz t su (pll) pll frequency synthesizer stabilization wait time v cc1 =5.5v 20 ms v cc1 =3.0v 50 ms main clock input oscillation frequency 16.0 0.0 f(xin) operating maximum frequency [mhz] vcc1[v] (main clock: no division) 5.5 3.0 10.0 2.7 20 x v cc1 -44mhz pll clock oscillation frequency 24.0 0.0 f(pll) operating maximum frequency [mhz] vcc1[v] (pll clock oscillation) 5.5 10.0 2.7 3.0 46.67 x v cc1 -116mhz m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 43 of 96 rej03b0001-0241 notes: 1. referenced to v cc1 =av cc =v ref =3.3 to 5.5v, v ss =av ss =0v at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified. 2. if v cc1 > v cc2 , do not use an0_0 to an0_7 and an2_0 to an2_7 as analog input pins. 3. ad frequency must be 12 mhz or le ss. and divide the fad if v cc1 is less than 4.0v, and ad frequency into 10 mhz or less. 4. when sample & hold is disabled, ad frequency must be 250 khz or more, in addition to the limitation in note 3. when sample & hold is enabled, ad frequency must be 1mhz or more, in addition to the limitation in note 3. table 5.4 a/d conversion characteristics (1) symbol parameter measuring condition standard unit min. typ. max. ? resolution v ref =v cc1 10 bits inl integral non-linearity error 10bit v ref = v cc1 = 5v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb external operation amp connection mode 7 lsb v ref = v cc1 = 3.3v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 5 lsb external operation amp connection mode 7 lsb 8bit v ref =v cc1 =5v, 3.3v 2 lsb ? absolute accuracy 10bit v ref = v cc1 = 5v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb external operation amp connection mode 7 lsb v ref = v cc1 =3.3v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 5 lsb external operation amp connection mode 7 lsb 8bit v ref =v cc1 =5v, 3.3v 2 lsb ? tolerance level impedance 3 k ? dnl differential non-linearity error 1 lsb ? offset error 3 lsb ? gain error 3 lsb r ladder ladder resistance v ref =v cc1 10 40 k ? t conv 10-bit conversion time, sample & hold available v ref =v cc1 =5v, ad=12mhz 2.75 s t conv 8-bit conversion time, sample & hold available v ref =v cc1 =5v, ad=12mhz 2.33 s t samp sampling time 0.25 s v ref reference voltage 2.0 v cc1 v v ia analog input voltage 0 v ref v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 44 of 96 rej03b0001-0241 notes: 1. referenced to v cc1 =v ref =3.3 to 5.5v, v ss =av ss =0v at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified. 2. this applies when using one d/a converter, with the d/a r egister for the unused d/a converter set to ?00h?. the resistor ladder of the a/d converter is not included. also, when d/a register contents are not ?00h?, the i vref will flow even if vref id disconnected by the a/ d control register. table 5.5 d/a conversion characteristics (1) symbol parameter measuring condition standard unit min. typ. max. ? resolution 8bits ? absolute accuracy 1.0 % t su setup time 3 s r o output resistance 4 10 20 k ? i vref reference power supply input current (note 2) 1.5 ma m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 45 of 96 rej03b0001-0241 notes: 1. referenced to v cc1 =4.5 to 5.5v, 3.0 to 3.6v at topr = 0 to 60 c (d3, d5, u3, u5) unless otherwise specified. 2. n denotes the number of block erases. 3. program and erase endurance refers to the num ber of times a block erase can be performed. if the program and erase endurance is n (n=100, 1, 000, or 10,000), each bloc k can be erased n times. for example, if a 4 kbytes block a is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. data cannot be written to t he same address more than once without erasing the block. (rewrite prohibited) 4. maximum number of e/w cycles for which operation is guaranteed. 5. topr = -40 to 85 c (d3, d7, u3, u7) / -20 to 85 c (d5, d9, u5, u9). 6. referenced to v cc1 = 4.5 to 5.5v, 3.0 to 3.6v at t opr = -40 to 85 c (d7, u7) / -20 to 85 c (d9, u9) unless otherwise specified. 7. table 5.7 applies for block a or block 1 program and erase endurance > 1,000. otherwise, use table 5.6. 8. to reduce the number of program and erase endurance when wo rking with systems requiring numerous rewrites, write to unused word addresses within the block instead of rewrite. erase block only after all possi ble addresses are used. for example, an 8-word program can be written 256 times maximum before erase becomes necessary. maintaining an equal number of erasure between block a and block 1 will also improve efficiency. it is important to track the total number of times erasure is used. 9. should erase error occur during block erase, attempt to ex ecute clear status register command, then block erase command at least three times until erase error disappears. 10. set the pm17 bit in the pm1 register to ?1? (wait state) when executing more than 100 time s rewrites (d7, d9, u7 and u9). 11. customers desiring e/w failure rate information shoul d contact their renesas tec hnical support representative. table 5.6 flash memory version electrical characteristics (1) for 100 cycle products (d3, d5, u3, u5) symbol parameter standard unit min. typ. max. ? program and erase endurance (3) 100 cycle ? word program time (v cc1 =5.0v ) 25 200 s ? lock bit program time 25 200 s ? block erase time (v cc1 =5.0v ) 4-kbyte block 0.3 4 s ? 8-kbyte block 0.3 4 s ? 32-kbyte block 0.5 4 s ? 64-kbyte block 0.8 4 s ? erase all unlocked blocks time (2) 4n s t ps flash memory circuit stabilization wait time 15 s ? data hold time (5) 10 year table 5.7 flash memory versi on electrical characteristics (6) for 10,000 cycle products (d7, d9, u7, u9) (block a and block 1 (7) ) symbol parameter standard unit min. typ. max. ? program and erase endurance (3, 8, 9) 10,000 (4) cycle ? word program time (v cc1 =5.0v ) 25 s ? lock bit program time 25 s ? block erase time (v cc1 =5.0v ) 4-kbyte block 0.3 s t ps flash memory circuit stabilization wait time 15 s ? data hold time (5) 10 year table 5.8 flash memory version program / erase voltage and read operation voltage characteristics (at t opr = 0 to 60 c(d3, d5, u3, u5), t opr = -40 to 85 c(d7, u7) / t opr = -20 to 85 c(d9, u9)) flash program, erase voltage flash read operation voltage v cc1 = 3.3 v 0.3 v or 5.0 v 0.5 v v cc1 =2.7 to 5.5 v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 46 of 96 rej03b0001-0241 notes: 1. v det4 > v det3 . 2. where reset level detection voltage is less than 2.7 v, if the supply power voltage is greater than the reset level detection voltage, the microcomputer operates with f(bclk) 10mhz. 3. v det3r > v det3 is not guaranteed. 4. the voltage detection circuit is desi gned to use when vcc1 is set to 5v. notes: 1. when v cc1 = 5v. table 5.9 low voltage detection circuit electrical characteristics symbol parameter measuring condition standard unit min. typ. max. v det4 low voltage detection voltage (1) v cc1 =0.8v to 5.5v 3.3 3.8 4.4 v v det3 reset level detection voltage (1, 2) 2.2 2.8 3.6 v v det4 -v det3 electric potential diffe rence of low voltage detection and reset level detection 0.3 v v det3s low voltage reset retention voltage 0.8 v v det3r low voltage reset release voltage (3) 2.2 2.9 4.0 v table 5.10 power supply circuit timing characteristics symbol parameter measuring condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during powering-on v cc1 =2.7v to 5.5v 2 ms t d(r-s) stop release time 150 s t d(w-s) low power dissipation mode wait mode release time 150 s t d(s-r) brown-out detection reset (hardware reset 2) release wait time v cc1 =v det3r to 5.5v 6 (1) 20 ms t d(e-a) low voltage detection circuit operation start time v cc1 =2.7v to 5.5v 20 s m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 47 of 96 rej03b0001-0241 figure 5.1 power supply circuit timing diagram t d(p-r) v cc1 cpu clock t d(p-r) time for internal power supply stabilization during powering-on interrupt for (a) stop mode release or (b) wait mode release cpu clock t d(r-s) (a) (b) t d(w-s) t d(r-s) stop release time t d(w-s) low power dissipation mode wait mode release time t d(s-r) v det3r v cc1 cpu clock t d(s-r) low voltage detection reset (hardware reset 2) release wait time vc26, vc27 t d(e-a) t d(e-a) low voltage detection circuit operation start time stop operate recommended operation voltage low voltage detection circuit m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 48 of 96 rej03b0001-0241 v cc1 =v cc2 =5v notes: 1. referenced to v cc1 =v cc2 =4.2 to 5.5v, v ss = 0v at t opr = ? 20 to 85 c / ? 40 to 85 c, f(bclk)=24mhz unless otherwise specified. 2. where the product is used at v cc1 = 5 v and v cc2 = 3 v, refer to the 3 v version value for the pin specified value on v cc2 port side. 3. there is no external connections for port p1_0 to p1_7, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. table 5.11 electrical characteristics (1) (1) symbol parameter measuring condition standard unit min. typ. max. v oh high output voltage (3) p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i oh = ? 5ma v cc1 ? 2.0 v cc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i oh = ? 5ma (2) v cc2 ? 2.0 v cc2 v oh high output voltage (3) p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 oh = ? 200 a v cc1 ? 0.3 v cc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i oh = ? 200 a (2) v cc2 ? 0.3 v cc2 v oh high output voltage xout highpower i oh = ? 1ma v cc1 ? 2.0 v cc1 v lowpower i oh = ? 0.5ma v cc1 ? 2.0 v cc1 high output voltage xcout highpower with no load applied 2.5 v lowpower with no load applied 1.6 v ol low output voltage (3) p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i ol =5ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i ol =5ma (2) 2.0 v ol low output voltage (3) p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i ol =200 a 0.45 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i ol =200 a (2) 0.45 v ol low output voltage xout highpower i ol =1ma 2.0 v lowpower i ol =0.5ma 2.0 low output voltage xcout highpower with no load applied 0 v lowpower with no load applied 0 v t+- v t- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int5 , nmi , adtrg , cts0 to cts2 , clk0 to clk4, ta0out to ta4out, ki0 to ki3 , rxd0 to rxd2, scl0 to scl2, sda0 to sda2, sin3, sin4 0.2 1.0 v v t+- v t- hysteresis reset 0.2 2.5 v i ih high input current (3) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, xin, reset , cnvss, byte v i =5v 5.0 a i il low input current (3) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7,p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, xin, reset , cnvss, byte v i =0v ? 5.0 a r pullup pull-up resistance (3) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7,p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 v i =0v 30 50 170 k ? r fxin feedback resistance xin 1.5 m ? r fxcin feedback resistance xcin 15 m ? v ram ram retention voltage at stop mode 2.0 v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 49 of 96 rej03b0001-0241 notes: 1. referenced to v cc1 =v cc2 =4.2 to 5.5v, v ss = 0v at t opr = ? 20 to 85 c / ? 40 to 85 c, f(bclk)=24mhz unless otherwise specified. 2. with one timer operated using fc32. 3. this indicates the memory in whic h the program to be executed exists. 4. i det is dissipation current when the following bi t is set to ?1? (detection circuit enabled). i det4 : vc27 bit in the vcr2 register i det3 : vc26 bit in the vcr2 register table 5.12 electrical characteristics (2) (1) symbol parameter measuring condition standard unit min. typ. max. i cc power supply current (v cc1 =v cc2 =4.0v to 5.5v) in single-chip mode, the output pins are open and other pins are v ss mask rom f(bclk)=24mhz no division, pll operation 14 20 ma no division, on-chip oscillation 1ma flash memory f(bclk)=24mhz, no division, pll operation 18 27 ma no division, on-chip oscillation 1.8 ma flash memory program f(bclk)=10mhz, vcc1=5.0v 15 ma flash memory erase f(bclk)=10mhz, vcc1=5.0v 25 ma mask rom f(xcin)=32khz low power dissipation mode, rom (3) 25 a flash memory f(bclk)=32khz low power dissipation mode, ram (3) 25 a f(bclk)=32khz low power dissipation mode, flash memory (3) 420 a on-chip oscillation, wait mode 50 a mask rom flash memory f(bclk)=32khz wait mode (2) , oscillation capability high 7.5 a f(bclk)=32khz wait mode (2) , oscillation capability low 2.0 a stop mode topr =25 c 0.8 3.0 a i det4 low voltage detection dissipation current (4) 0.7 4 a i det3 reset area detection dissipation current (4) 1.2 8 a m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 50 of 96 rej03b0001-0241 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. the condition is v cc1 =v cc2 =3.0 to 5.0v. notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is ?2? for 1-wait setting, ?3? for 2- wait setting and ?4? for 3-wait setting. 3. calculated according to the bclk frequency as follows: n is ?2? for 2-wait setting, ?3? for 3-wait setting. table 5.13 external clock input (xin input) (1) symbol parameter standard unit min. max. t c external clock input cycle time 62.5 ns t w(h) external clock input high pulse width 25 ns t w(l) external clock input low pulse width 25 ns t r external clock rise time 15 ns t f external clock fall time 15 ns table 5.14 memory expansion mode and microprocessor mode symbol parameter standard unit min. max. t ac1(rd-db) data input access time (for setting with no wait) (note 1) ns t ac2(rd-db) data input access time (for setting with wait) (note 2) ns t ac3(rd-db) data input access time (when accessing multiplex bus area) (note 3) ns t su(db-rd) data input setup time 40 ns t su(rdy-bclk) rdy input setup time 30 ns t su(hold-bclk) hold input setup time 40 ns t h(rd-db) data input hold time 0 ns t h(bclk-rdy) rdy input hold time 0 ns t h(bclk-hold) hold input hold time 0 ns 0.5x10 9 fbclk () ----------------------- -45ns [] ? n0.5 ? () x 10 9 fbclk () ------------------------------------ -45ns [] ? n0.5 ? () x 10 9 fbclk () ------------------------------------ -45ns [] ? m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 51 of 96 rej03b0001-0241 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.15 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 100 ns t w(tah) taiin input high pulse width 40 ns t w(tal) taiin input low pulse width 40 ns table 5.16 timer a input (gating input in timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 400 ns t w(tah) taiin input high pulse width 200 ns t w(tal) taiin input low pulse width 200 ns table 5.17 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 200 ns t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns table 5.18 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns table 5.19 timer a input (counter increment/ decrement input in event counter mode) symbol parameter standard unit min. max. t c(up) taiout input cycle time 2000 ns t w(uph) taiout input high pulse width 1000 ns t w(upl) taiout input low pulse width 1000 ns t su(up-tin) taiout input setup time 400 ns t h(tin-up) taiout input hold time 400 ns table 5.20 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 800 ns t su(tain-taout) taiout input setup time 200 ns t su(taout-tain) taiin input setup time 200 ns m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 52 of 96 rej03b0001-0241 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.21 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time (counted on one edge) 100 ns t w(tbh) tbiin input high pulse width (counted on one edge) 40 ns t w(tbl) tbiin input low pulse width (counted on one edge) 40 ns t c(tb) tbiin input cycle time (counted on both edges) 200 ns t w(tbh) tbiin input high pulse width (counted on both edges) 80 ns t w(tbl) tbiin input low pulse width (counted on both edges) 80 ns table 5.22 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns table 5.23 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns table 5.24 a/d trigger input symbol parameter standard unit min. max. t c(ad) adtrg input cycle time 1000 ns t w(adl) adtrg input low pulse width 125 ns table 5.25 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ns t w(ckh) clki input high pulse width 100 ns t w(ckl) clki input low pulse width 100 ns t d(c-q) txdi output delay time 80 ns t h(c-q) txdi hold time 0 ns t su(d-c) rxdi input setup time 70 ns t h(c-d) rxdi input hold time 90 ns table 5.26 external interrupt inti input symbol parameter standard unit min. max. t w(inh) inti input high pulse width 250 ns t w(inl) inti input low pulse width 250 ns m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 53 of 96 rej03b0001-0241 v cc1 =v cc2 =5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: f(bclk) is 12.5mhz or less. 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output ?l? level is t = ? 30pf x 1k ? x in(1 ? 0.2v cc2 / v cc2 ) = 6.7ns. figure 5.2 ports p0 to p14 measurement circuit table 5.27 memory expansion and micropro cessor modes (for setting with no wait) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.2 25 ns t h(bclk-ad) address output hold time (in relation to bclk) 4 ns t h(rd-ad) address output hold time (in relation to rd) 0 ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 4 ns t d(bclk-ale) ale signal output delay time 15 ns t h(bclk-ale) ale signal output hold time ? 4ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 4ns t d(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns t d(bclk-hlda) hlda output delay time 40 ns 0.5x10 9 fbclk () ----------------------- -40ns [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p11 p12 p13 p14 m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 54 of 96 rej03b0001-0241 v cc1 =v cc2 =5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output ?l? level is t = ? 30pf x 1k ? x in(1 ? 0.2v cc2 / v cc2 ) = 6.7ns. table 5.28 memory expansion and microprocessor modes (for 1- to 3-wait setting and external area access) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.2 25 ns t h(bclk-ad) address output hold time (in relation to bclk) 4 ns t h(rd-ad) address output hold time (in relation to rd) 0 ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 4 ns t d(bclk-ale) ale signal output delay time 15 ns t h(bclk-ale) ale signal output hold time -4 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 4ns t d(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns t d(bclk-hlda) hlda output delay time 40 ns n0.5 ? () x10 9 fbclk () ------------------------------------ 4 0 n s [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c n is ?1? for 1-wait setting, ?2? for 2-wait setting and ?3? for 3-wait setting. (bclk) is 12.5mhz or less. m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 55 of 96 rej03b0001-0241 v cc1 =v cc2 =5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is ?2? for 2-wait setting, ?3? for 3-wait setting. 3. calculated according to the bclk frequency as follows: 4. calculated according to the bclk frequency as follows: table 5.29 memory expansion and microprocessor modes (for 2- to 3-wait setting, external area access and multiplex bus selection) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.2 25 ns t h(bclk-ad) address output hold time (in relation to bclk) 4 ns t h(rd-ad) address output hold time (in relation to rd) (note 1) ns t h(wr-ad) address output hold time (in relation to wr) (note 1) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 4 ns t h(rd-cs) chip select output hold time (in relation to rd) (note 1) ns t h(wr-cs) chip select output hold time (in relation to wr) (note 1) ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) 4 ns t d(db-wr) data output delay time (in relation to wr) (note 2) ns t h(wr-db) data output hold time (in relation to wr) (note 1) ns t d(bclk-hlda) hlda output delay time 40 ns t d(bclk-ale) ale signal output delay time (in relation to bclk) 15 ns t h(bclk-ale) ale signal output hold time (in relation to bclk) ? 4ns t d(ad-ale) ale signal output delay time (in relation to address) (note 3) ns t h(ad-ale) ale signal output hold time (i n relation to address) (note 4) ns t d(ad-rd) rd signal output delay from the end of address 0 ns t d(ad-wr) wr signal output delay from the end of address 0 ns t dz(rd-ad) address output floating start time 8 ns 0.5x10 9 fbclk () ----------------------- -10ns [] ? n0.5 ? () x10 9 fbclk () ------------------------------------ 4 0 n s [] ? 0.5x10 9 fbclk () ----------------------- -25ns [] ? 0.5x10 9 fbclk () ----------------------- -15ns [] ? m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 56 of 96 rej03b0001-0241 figure 5.3 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on fa lling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 57 of 96 rej03b0001-0241 figure 5.4 timing diagram (2) t su(d-c) clk i txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 58 of 96 rej03b0001-0241 figure 5.5 timing diagram (3) memory expansion mo de, microprocessor mode ( effective for setting with wait ) bclk hold input hlda input measuring conditions : v cc1 =v cc2 =5v input timing voltage : determined with v il =1.0v, v ih =4.0v output timing voltage : determined with v ol =2.5v, v oh =2.5v p0, p1, p2, p3, p4, p5_0 to p5_2 (1) ( common to setting with wait and setting without wait ) notes: 1. these pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit in pm0 register and pm11 bit in pm1 register. t h(bclk ? hold) t su(hold ? bclk) t d(bclk ? hlda) t d(bclk ? hlda) hi ? z rdy input t su(rdy ? bclk) t h(bclk ? rdy) rd bclk (separate bus) (multiplexed bus) wr, wrl, wrh rd (separate bus) wr, wrl, wrh (multiplexed bus) v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 59 of 96 rej03b0001-0241 figure 5.6 timing diagram (4) bclk csi t d(bclk-cs) 25ns.max adi 25ns.max ale 25ns.max -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe t cyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 40ns.min t ac1(rd-db) memory expansion mode, microprocessor mode ( for setting with no wait ) measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v wr, wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 t cyc -40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 t cyc -45)ns.max t cyc = 1 f(bclk) (0.5 t cyc -10)ns.min (0.5 t cyc -10)ns.min v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 60 of 96 rej03b0001-0241 figure 5.7 timing diagram (5) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t su(db-rd) 40ns.min t h(rd-db) 0ns.min t cyc bhe read timing wr, wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 t cyc -40)ns.min (0.5 t cyc -10)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode, microprocessor mode ( for 1-wait setting and external area access ) measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v (1.5 t cyc -45)ns.max t cyc = f(bclk) 1 (0.5 tcyc-10)ns.min v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 61 of 96 rej03b0001-0241 figure 5.8 timing diagram (6) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 2-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 t cyc -40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 t cyc -10)ns.min measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v t ac2(rd-db) (2.5 t cyc -45)ns.max tcyc = 1 f(bclk) v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 62 of 96 rej03b0001-0241 figure 5.9 timing diagram (7) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 3-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 t cyc -40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 t cyc -10)ns.min measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v t ac2(rd-db) (3.5 t cyc -45)ns.max t cyc = 1 f(bclk) t cyc v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 63 of 96 rej03b0001-0241 figure 5.10 timing diagram (8) memory expansion mode, microprocessor mode ( for 1- or 2-wait setting, external area access and multiplex bus selection ) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale t h(bclk-ale) ? 4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) ? 4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address (0.5 t cyc -10)ns.min address data input 40ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) t d(bclk-rd) (0.5 t cyc -10)ns.min t h(wr-cs) address t d(ad-ale) (0.5 t cyc -25)ns.min (1.5 t cyc -40)ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) (0.5 t cyc -25)ns.min address 25ns.max t su(db-rd) t ac3(rd-db) (0.5 t cyc -10)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v t h(ale-ad) (1.5 t cyc -45)ns.max (0.5 t cyc -15)ns.min v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 64 of 96 rej03b0001-0241 figure 5.11 timing diagram (9) read timing write timing memory expansion mode, microprocessor mode ( for 3-wait setting, external area access and multiplex bus selection ) bclk csi ale rd adi /dbi adi bhe (no multiplex) bclk csi ale adi /dbi t cyc t d(bclk-ad) 25ns.max t cyc data output t h(bclk-cs) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max t h(bclk-rd) 0ns.min t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 t cyc -10)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 t cyc -10)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 25ns.max t d(bclk-wr) 25ns.max t h(wr-db) (0.5 t cyc -10)ns.min data input address address adi bhe (no multiplex) wr, wrl wrh measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v t d(ad-ale) (0.5 t cyc -25)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 40ns.max (0.5 t cyc -10)ns.min t h(wr-cs) t d(db-wr) (2.5 tcyc-40)ns.min t d(ad-wr) 0ns.min t h(rd-cs) (0.5 t cyc -10)ns.min t d(ad-ale) (0.5 t cyc -25)ns.min t h(ale-ad) (2.5 t cyc -45)ns.max t cyc = 1 f(bclk) (0.5 tcyc-15)ns.min t h(bclk-ale) -4ns.min v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 65 of 96 rej03b0001-0241 v cc1 =v cc2 =3v notes: 1. referenced to v cc1 = v cc2 = 2.7 to 3.3v, v ss = 0v at topr = ? 20 to 85 c / ? 40 to 85 c, f(xin)=10mhz no wait unless otherwise specified. 2. v cc1 for the port p6 to p11 and p14, and v cc2 for the port p0 to p5 and p12 to p13 3. there is no external connections for port p1_0 to p1_7, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. table 5.30 electrical characteristics (1) (1) symbol parameter measuring condition standard unit min. typ. max. v oh high output voltage (3) p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i oh = ? 1ma v cc1 ? 0.5 v cc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i oh = ? 1ma (2) v cc2 ? 0.5 v cc2 v oh high output voltage xout highpower i oh = ?0. 1ma v cc1 ? 0.5 v cc1 v lowpower i oh = ? 50 a v cc1 ? 0.5 v cc1 high output voltage xc out highpower with no load applied 2.5 v lowpower with no load applied 1.6 v ol low output voltage (3) p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i ol =1ma 0.5 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i ol =1ma (2) 0.5 v ol low output voltage xout highpower i ol =0.1ma 0.5 v lowpower i ol =50 a 0.5 low output voltage xcout highpower with no load applied 0 v lowpower with no load applied 0 v t+- v t- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int5 , nmi , adtrg , cts0 to cts2 , clk0 to clk4, ta0out to ta4out, ki0 to ki3 , rxd0 to rxd2, scl0 to scl2, sda0 to sda2, sin3, sin4 0.2 0.8 v v t+- v t- hysteresis reset 0.2 (0.7) 1.8 v i ih high input current (3) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, xin, reset , cnvss, byte v i =3v 4.0 a i il low input current (3) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, xin, reset , cnvss, byte v i =0v ? 4.0 a r pullup pull-up resistance (3) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7,p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 v i =0v 50 100 500 k ? r fxin feedback resistance xin 3.0 m ? r fxcin feedback resistance xcin 25 m ? v ram ram retention voltage at stop mode 2.0 v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 66 of 96 rej03b0001-0241 notes: 1. referenced to v cc1 =v cc2 =2.7 to 3.3v, v ss = 0v at t opr = ? 20 to 85 c / ? 40 to 85 c, f(bclk)=10mhz unless otherwise specified. 2. with one timer operated using fc32. 3. this indicates the memory in whic h the program to be executed exists. 4. i det is dissipation current when the following bi t is set to ?1? (detection circuit enabled). i det4 : vc27 bit in the vcr2 register i det3 : vc26 bit in the vcr2 register table 5.31 electrical characteristics (2) (1) symbol parameter measuring condition standard unit min. typ. max. i cc power supply current (v cc1 =v cc2 =2.7v to 3.6v) in single-chip mode, the output pins are open and other pins are v ss mask rom f(bclk)=10mhz no division 811ma no division, on-chip oscillation 1ma flash memory f(bclk)=10mhz, no division 813ma no division, on-chip oscillation 1.8 ma flash memory program f(bclk)=10mhz, vcc1=3.0v 12 ma flash memory erase f(bclk)=10mhz, vcc1=3.0v 22 ma mask rom f(xcin)=32khz low power dissipation mode, rom (3) 25 a flash memory f(bclk)=32khz low power dissipation mode, ram (3) 25 a f(bclk)=32khz low power dissipation mode, flash memory (3) 420 a on-chip oscillation, wait mode 45 a mask rom flash memory f(bclk)=32khz wait mode (2) , oscillation capability high 6.0 a f(bclk)=32khz wait mode (2) , oscillation capability low 1.8 a stop mode topr =25 c 0.7 3.0 a i det4 low voltage detection dissipation current (4) 0.6 4 a i det3 reset area detection dissipation current (4) 0.4 2 a m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 67 of 96 rej03b0001-0241 v cc1 =v cc2 =3v timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. the condition is v cc1 =v cc2 =2.7 to 3.0v. 2. calculated according to the v cc1 voltage as follows: [ns] 3. calculated according to the v cc1 voltage as follows: [ns] 4. calculated according to the v cc1 voltage as follows: [ns] notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is ?2? for 1-wait setting, ?3? for 2- wait setting and ?4? for 3-wait setting. 3. calculated according to the bclk frequency as follows: n is ?2? for 2-wait setting, ?3? for 3-wait setting. table 5.32 external clock input (xin input) (1) symbol parameter standard unit min. max. t c external clock input cycle time (note 2) ns t w(h) external clock input high pulse width (note 3) ns t w(l) external clock input low pulse width (note 3) ns t r external clock rise time (note 4) ns t f external clock fall time (note 4) ns table 5.33 memory expansion mode and microprocessor mode symbol parameter standard unit min. max. t ac1(rd-db) data input access time (for setting with no wait) (note 1) ns t ac2(rd-db) data input access time (for setting with wait) (note 2) ns t ac3(rd-db) data input access time (when accessing multiplex bus area) (note 3) ns t su(db-rd) data input setup time 50 ns t su(rdy-bclk) rdy input setup time 40 ns t su(hold-bclk) hold input setup time 50 ns t h(rd-db) data input hold time 0 ns t h(bclk-rdy) rdy input hold time 0 ns t h(bclk-hold) hold input hold time 0 ns 10 6 ? 20 v cc2 44 ? --------------------------------------- - 10 6 ? 20 v cc1 44 ? --------------------------------------- - 0.4 10 ? v cc1 45 + 0.5x10 9 fbclk () ----------------------- -60ns [] ? n0.5 ? () x10 9 fbclk () ------------------------------------ 6 0 n s [] ? n0.5 ? () x10 9 fbclk () ------------------------------------ 6 0 n s [] ? m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 68 of 96 rej03b0001-0241 v cc1 =v cc2 =3v timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.34 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 150 ns t w(tah) taiin input high pulse width 60 ns t w(tal) taiin input low pulse width 60 ns table 5.35 timer a input (gating input in timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 600 ns t w(tah) taiin input high pulse width 300 ns t w(tal) taiin input low pulse width 300 ns table 5.36 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 300 ns t w(tah) taiin input high pulse width 150 ns t w(tal) taiin input low pulse width 150 ns table 5.37 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. t w(tah) taiin input high pulse width 150 ns t w(tal) taiin input low pulse width 150 ns table 5.38 timer a input (counter increment/ decrement input in event counter mode) symbol parameter standard unit min. max. t c(up) taiout input cycle time 3000 ns t w(uph) taiout input high pulse width 1500 ns t w(upl) taiout input low pulse width 1500 ns t su(up-tin) taiout input setup time 600 ns t h(tin-up) taiout input hold time 600 ns table 5.39 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 2 s t su(tain-taout) taiout input setup time 500 ns t su(taout-tain) taiin input setup time 500 ns m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 69 of 96 rej03b0001-0241 v cc1 =v cc2 =3v timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.40 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time (counted on one edge) 150 ns t w(tbh) tbiin input high pulse width (counted on one edge) 60 ns t w(tbl) tbiin input low pulse width (counted on one edge) 60 ns t c(tb) tbiin input cycle time (counted on both edges) 300 ns t w(tbh) tbiin input high pulse width (counted on both edges) 120 ns t w(tbl) tbiin input low pulse width (counted on both edges) 120 ns table 5.41 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 600 ns t w(tbh) tbiin input high pulse width 300 ns t w(tbl) tbiin input low pulse width 300 ns table 5.42 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 600 ns t w(tbh) tbiin input high pulse width 300 ns t w(tbl) tbiin input low pulse width 300 ns table 5.43 a/d trigger input symbol parameter standard unit min. max. t c(ad) adtrg input cycle time 1500 ns t w(adl) adtrg input low pulse width 200 ns table 5.44 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ns t w(ckh) clki input high pulse width 150 ns t w(ckl) clki input low pulse width 150 ns t d(c-q) txdi output delay time 160 ns t h(c-q) txdi hold time 0 ns t su(d-c) rxdi input setup time 100 ns t h(c-d) rxdi input hold time 90 ns table 5.45 external interrupt inti input symbol parameter standard unit min. max. t w(inh) inti input high pulse width 380 ns t w(inl) inti input low pulse width 380 ns m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 70 of 96 rej03b0001-0241 v cc1 =v cc2 =3v switching characteristics (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: f(bclk) is 12.5mhz or less. 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output ?l? level is t = ? 30pf x 1k ? x in(1 ? 0.2v cc2 / v cc2 ) = 6.7ns. figure 5.12 ports p0 to p14 measurement circuit table 5.46 memory expansion and micropro cessor modes (for setting with no wait) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.12 30 ns t h(bclk-ad) address output hold time (in relation to bclk) 4 ns t h(rd-ad) address output hold time (in relation to rd) 0 ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 30 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 4 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time ? 4ns t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 4ns t d(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns t d(bclk-hlda) hlda output delay time 40 ns 0.5x10 9 fbclk () ----------------------- -40ns [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p11 p12 p13 p14 m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 71 of 96 rej03b0001-0241 v cc1 =v cc2 =3v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output ?l? level is t = ? 30pf x 1k ? x in(1 ? 0.2v cc2 / v cc2 ) = 6.7ns. table 5.47 memory expansion and microprocessor modes (for 1- to 3-wait setting and external area access) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.12 30 ns t h(bclk-ad) address output hold time (in relation to bclk) 4 ns t h(rd-ad) address output hold time (in relation to rd) 0 ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 30 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 4 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time -4 ns t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 4ns t d(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns t d(bclk-hlda) hlda output delay time 40 ns n0.5 ? () x10 9 fbclk () ------------------------------------ 4 0 n s [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c n is ?1? for 1-wait setting, ?2? for 2-wait setting and ?3? for 3-wait setting. (bclk) is 12.5mhz or less. m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 72 of 96 rej03b0001-0241 v cc1 =v cc2 =3v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is ?2? for 2-wait setting, ?3? for 3-wait setting. 3. calculated according to the bclk frequency as follows: 4. calculated according to the bclk frequency as follows: table 5.48 memory expansion and microprocessor modes (for 2- to 3-wait setting, external area access and multiplex bus selection) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.12 50 ns t h(bclk-ad) address output hold time (in relation to bclk) 4 ns t h(rd-ad) address output hold time (in relation to rd) (note 1) ns t h(wr-ad) address output hold time (in relation to wr) (note 1) ns t d(bclk-cs) chip select output delay time 50 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 4 ns t h(rd-cs) chip select output hold time (in relation to rd) (note 1) ns t h(wr-cs) chip select output hold time (in relation to wr) (note 1) ns t d(bclk-rd) rd signal output delay time 40 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 40 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 50 ns t h(bclk-db) data output hold time (in relation to bclk) 4 ns t d(db-wr) data output delay time (in relation to wr) (note 2) ns t h(wr-db) data output hold time (in relation to wr) (note 1) ns t d(bclk-hlda) hlda output delay time 40 ns t d(bclk-ale) ale signal output delay time (in relation to bclk) 25 ns t h(bclk-ale) ale signal output hold time (in relation to bclk) ? 4ns t d(ad-ale) ale signal output delay time (in relation to address) (note 3) ns t h(ad-ale) ale signal output hold time (i n relation to address) (note 4) ns t d(ad-rd) rd signal output delay from the end of address 0 ns t d(ad-wr) wr signal output delay from the end of address 0 ns t dz(rd-ad) address output floating start time 8 ns 0.5x10 9 fbclk () ----------------------- -10ns [] ? 0.5x10 9 fbclk () ----------------------- - 50 ns [] ? 0.5x10 9 fbclk () ----------------------- - 40 ns [] ? 0.5x10 9 fbclk () ----------------------- -15ns [] ? m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 73 of 96 rej03b0001-0241 figure 5.13 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c v cc1 =v cc2 =3v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 74 of 96 rej03b0001-0241 figure 5.14 timing diagram (2) t su(d-c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) inti input t d(c-q) t h(c-d) t h(c-q) v cc1 =v cc2 =3v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 75 of 96 rej03b0001-0241 figure 5.15 timing diagram (3) memory expansion mode, microprocessor mode (effective for setting with wait) bclk hold input hlda output measuring conditions : v cc1 =v cc2 =3v input timing voltage : determined with v il =0.6v, v ih =2.4v output timing voltage : determined with v ol =1.5v, v oh =1.5v p0, p1, p2, p3, p4, p5_0 to p5_2 (1) (common to setting with wait and setting without wait) notes: 1. these pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit in pm0 register and pm11 bit in pm1 register. t h(bclk ? hold) t su(hold ? bclk) t d(bclk ? hlda) t d(bclk ? hlda) hi ? z rdy input t su(rdy ? bclk) t h(bclk ? rdy) rd bclk (separate bus) (multiplexed bus) wr, wrl, wrh rd (separate bus) wr, wrl, wrh (multiplexed bus) v cc1 =v cc2 =3v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 76 of 96 rej03b0001-0241 figure 5.16 timing diagram (4) bclk csi t d(bclk-cs) 30ns.max adi 30ns.max ale 30ns.max -4ns.min rd 30ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe t cyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 50ns.min t ac1(rd-db) memory expansion mode , microprocessor mode ( for setting with no wait ) measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v wr, wrl, wrh 30ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 t cyc -40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 t cyc -60)ns.max t cyc = 1 f(bclk) (0.5 t cyc -10)ns.min (0.5 t cyc -10)ns.min v cc1 =v cc2 =3v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 77 of 96 rej03b0001-0241 figure 5.17 timing diagram (5) bclk csi t d(bclk ? cs) 30ns.max adi t d(bclk ? ad) 30ns.max ale 30ns.max t h(bclk ? ale) ? 4ns.min rd 30ns.max t h(bclk ? rd) 0ns.min t h(bclk ? ad) 4ns.min t h(bclk ? cs) 4ns.min hi ? z dbi t su(db ? rd) 50ns.min t h(rd ? db) 0ns.min t cyc bhe read timing wr,wrl, wrh 30ns.max t h(bclk ? wr) 0ns.min bclk csi t d(bclk ? cs) 30ns.max adi t d(bclk ? ad) 30ns.max ale 30ns.max t d(bclk ? ale) t h(bclk ? ale) ? 4ns.min t h(bclk ? ad) 4ns.min t h(bclk ? cs) 4ns.min t cyc t h(wr ? ad) bhe t d(bclk ? db) 40ns.max 4ns.min t h(bclk ? db) t d(db ? wr) (0.5 t cyc ? 40)ns.min (0.5 t cyc ? 10)ns.min t h(wr ? db) dbi write timing t d(bclk ? ale) t d(bclk ? rd) (0.5 t cyc ? 10)ns.min t d(bclk ? wr) 0ns.min t h(rd ? ad) t ac2(rd ? db) hi ? z memory expansion mode, microprocessor mode ( for 1-wait setting and external area access ) (1.5 t cyc ? 60)ns.max t cyc = 1 f(bclk) v cc1 =v cc2 =3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 78 of 96 rej03b0001-0241 figure 5.18 timing diagram (6) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 2-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 30ns.max hi-z t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc hi-z t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 30ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 t cyc -10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 t cyc -40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 t cyc -10)ns.min t ac2(rd-db) (2.5 t cyc -60)ns.max t cyc = 1 f(bclk) v cc1 =v cc2 =3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 79 of 96 rej03b0001-0241 figure 5.19 timing diagram (7) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 3-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 30ns.max hi-z t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc hi-z t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 30ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 t cyc -10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 t cyc -40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 tcyc-10)ns.min t ac2(rd-db) (3.5 t cyc -60)ns.max t cyc = 1 f(bclk) v cc1 = v cc2 = 3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 80 of 96 rej03b0001-0241 figure 5.20 timing diagram (8) memory expansion mode, microprocessor mode ( for 2-wait setting, external area access and multiplex bus selection ) bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale t h(bclk-ale) -4ns.min rd 40ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 40ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale 40ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 50ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address (0.5 t cyc -10)ns.min address data input 50ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) t d(bclk-rd) (0.5 t cyc -10)ns.min t h(wr-cs) address t d(ad-ale) (0.5 t cyc -40)ns.min (1.5 t cyc -50)ns.min (0.5 t cyc -10)ns.min t d(bclk-ale) (0.5 t cyc -40)ns.min address 40ns.max t su(db-rd) t ac3(rd-db) (0.5 t cyc -10)ns.min t h(ale-ad) t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min (1.5 t cyc -60)ns.max t cyc = 1 f(bclk) (0.5 t cyc -15)ns.min v cc1 =v cc2 =3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 81 of 96 rej03b0001-0241 figure 5.21 timing diagram (9) read timing write timing memory expansion mode, microprocessor mode ( for 3-wait setting, external area access and multiplex bus selection ) bclk csi ale rd adi /dbi adi bhe (no multiplex) bclk csi ale adi /dbi t cyc t d(bclk-ad) 40ns.max t cyc data output t h(bclk-cs) 6ns.min t d(bclk-cs) 40ns.max t d(bclk-ale) 40ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 40ns.max t h(bclk-rd) 0ns.min t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 t cyc -10)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 40ns.max t d(bclk-ad) 40ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 t cyc -10)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 40ns.max t d(bclk-wr) 40ns.max t h(wr-db) (0.5 t cyc -10)ns.min data input address address adi bhe (no multiplex) wr, wrl wrh t h(ale-ad) t d(ad-ale) (0.5 t cyc -40)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 50ns.max (0.5 t cyc -10)ns.min t h(wr-cs) t d(db-wr) (2.5 t cyc -50)ns.min t d(ad-wr) 0ns.min t h(rd-cs) (0.5 t cyc -10)ns.min t d(ad-ale) (0.5 t cyc -40)ns.min (2.5 t cyc -60)ns.max t cyc = 1 f(bclk) t h(bclk-ale) -4ns.min (0.5 t cyc -15)ns.min v cc1 =v cc2 =3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 82 of 96 rej03b0001-0241 5.2 electrical charac teristics (m16c/62pt) notes: 1. there is no external connections for port p1_0 to p1_7, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. 2. t version = ? 40 to 85 c, v version= ? 40 to 125 c. table 5.49 absolute maximum ratings symbol parameter condition rated value unit v cc1 , v cc2 supply voltage v cc1 =v cc2= av cc ? 0.3 to 6.5 v av cc analog supply voltage v cc1 =v cc2= av cc ? 0.3 to 6.5 v v i input voltage reset , cnvss, byte, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1, vref, xin ? 0.3 to v cc1 +0.3 (1) v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 ? 0.3 to v cc2 +0.3 (1) v p7_0, p7_1 ? 0.3 to 6.5 v v o output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1, xout ? 0.3 to v cc1 +0.3 (1) v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 ? 0.3 to v cc2 +0.3 (1) v p7_0, p7_1 ? 0.3 to 6.5 v p d power dissipation ? 40 c m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 84 of 96 rej03b0001-0241 notes: 1. referenced to v cc1 =av cc =v ref =4.0 to 5.5v, v ss =av ss =0v at t opr = ? 40 to 85 c / ? 40 to 125 c unless otherwise specified. t version = ? 40 to 85 c, v version = ? 40 to 125 c 2. ad frequency must be 12 mhz or less. 3. when sample & hold is disabled, ad frequency must be 250 khz or more, in addition to the limitation in note 2. when sample & hold is enabled, ad frequency must be 1mhz or more, in addition to the limitation in note 2. notes: 1. referenced to v cc1 =v ref =4.0 to 5.5v, v ss =av ss =0v at t opr = ? 40 to 85 c / ? 40 to 125 c unless otherwise specified. t version = ? 40 to 85 c, v version = ? 40 to 125 c 2. this applies when using one d/a converter, with the d/a r egister for the unused d/a converter set to ?00h?. the resistor ladder of the a/d converter is not included. also, when d/a register contents are not ?00h?, the i vref will flow even if vref id disconnected by the a/ d control register. table 5.51 a/d conversion characteristics (1) symbol parameter measuring condition standard unit min. typ. max. ? resolution v ref =v cc1 10 bits inl integral non-linearity error 10bit v ref = v cc1 = 5v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb external operation amp connection mode 7 lsb 8bit v ref =v cc1 =5v 2 lsb ? absolute accuracy 10bit v ref = v cc1 = 5v an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input, anex0, anex1 input 3 lsb external operation amp connection mode 7 lsb 8bit v ref =v cc1 =5v 2 lsb ? tolerance level impedance 3 k ? dnl differential non-linearity error 1 lsb ? offset error 3 lsb ? gain error 3 lsb r ladder ladder resistance v ref =v cc1 10 40 k ? t conv 10-bit conversion time, sample & hold function available v ref =v cc1 =5v, ad=12mhz 2.75 s t conv 8-bit conversion time, sample & hold function available v ref =v cc1 =5v, ad=12mhz 2.33 s t samp sampling time 0.25 s v ref reference voltage 2.0 v cc1 v v ia analog input voltage 0 v ref v table 5.52 d/a conversion characteristics (1) symbol parameter measuring condition standard unit min. typ. max. ? resolution 8bits ? absolute accuracy 1.0 % t su setup time 3 s r o output resistance 4 10 20 k ? i vref reference power supply input current (note 2) 1.5 ma m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 85 of 96 rej03b0001-0241 notes: 1. referenced to v cc1 =4.5 to 5.5v at t opr = 0 to 60 c unless otherwise specified. 2. n denotes the number of block erases. 3. program and erase endurance refers to the num ber of times a block erase can be performed. if the program and erase endurance is n (n=100, 1, 000, or 10,000), each bloc k can be erased n times. for example, if a 4 kbytes block a is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. data cannot be written to t he same address more than once without erasing the block. (rewrite prohibited) 4. maximum number of e/w cycles for which operation is guaranteed. 5. ta (ambient temperature)=55 c. as to the data hold time except ta=55 c, please contact renesas technology corp. or an authorized renesas technology corp. product distributor. 6. referenced to v cc1 = 4.5 to 5.5v at t opr = ? 40 to 85 c (b7, u7 (t version)) / ? 40 to 125 c (b7, u7 (v version)) unless otherwise specified. 7. table 5.54 applies for block a or block 1 program and erase endurance > 1,000. otherwise, use table 5.53. 8. to reduce the number of program and erase endurance when wo rking with systems requiring numerous rewrites, write to unused word addresses within the block instead of rewrite. erase block only after all possi ble addresses are used. for example, an 8-word program can be written 256 times maximum before erase becomes necessary. maintaining an equal number of erasure between block a and block 1 will also improve efficiency. it is important to track the total number of times erasure is used. 9. should erase error occur during block erase, attempt to ex ecute clear status register command, then block erase command at least three times until erase error disappears. 10. set the pm17 bit in the pm1 register to ?1? (wait stat e) when executing more than 100 times rewrites (b7 and u7). 11. customers desiring e/w failure rate information shoul d contact their renesas tec hnical support representative. table 5.53 flash memory version electrical characteristics (1) for 100 cycle products (b, u) symbol parameter standard unit min. typ. max. ? program and erase endurance (3) 100 cycle ? word program time (v cc1 =5.0v ) 25 200 s ? lock bit program time 25 200 s ? block erase time (v cc1 =5.0v ) 4-kbyte block 4 0.3 4 s ? 8-kbyte block 0.3 4 s ? 32-kbyte block 0.5 4 s ? 64-kbyte block 0.8 4 s ? erase all unlocked blocks time (2) 4n s t ps flash memory circuit stabilization wait time 15 s ? data hold time (5) 20 year table 5.54 flash memory version electrical characteristics (6) for 10,000 cycle products (b7, u7) (block a and block 1 (7) ) symbol parameter standard unit min. typ. max. ? program and erase endurance (3, 8, 9) 10,000 (4) cycle ? word program time (v cc 1=5.0v ) 25 s ? lock bit program time 25 s ? block erase time (v cc1 =5.0v ) 4-kbyte block 4 0.3 s t ps flash memory circuit stabilization wait time 15 s ? data hold time (5) 20 year table 5.55 flash memory version program/erase voltage and read operation voltage characteristics (at t opr = 0 to 60 c(b, u), topr = ? 40 to 85 c (b7, u7 (t version)) / ? 40 to 125 c (b7, u7 (v version)) flash program, erase voltage flash read operation voltage v cc1 = 5.0 v 0.5 v v cc1 =4.0 to 5.5 v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 86 of 96 rej03b0001-0241 figure 5.22 power supply circuit timing diagram table 5.56 power supply circuit timing characteristics symbol parameter measuring condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during powering-on v cc1 =4.0v to 5.5v 2 ms t d(r-s) stop release time 150 s t d(w-s) low power dissipation mode wait mode release time 150 s t d(p-r) v cc1 cpu clock cpu clock t d(r-s) (a) (b) t d(w-s) td(p-r) time for internal power supply stabilization during powering-on interrupt for (a) stop mode release or (b)wait mode release td(r-s) stop release time td(w-s) low power dissipation mode wait mode release time recommended operation voltage m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 87 of 96 rej03b0001-0241 v cc1 =v cc2 =5v notes: 1. referenced to v cc1 =v cc2 =4.0 to 5.5v, v ss = 0v at t opr = ? 40 to 85 c / ? 40 to 125 c, f(bclk)=24mhz unless otherwise specified. t version = ? 40 to 85 c, v version = ? 40 to 125 c. 2. there is no external connections for port p1_0 to p1_7, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. table 5.57 electrical characteristics (1) (1) symbol parameter measuring condition standard unit min. typ. max. v oh high output voltage (2) p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i oh = ? 5ma v cc1 ? 2.0 v cc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i oh = ? 5ma v cc2 ? 2.0 v cc2 v oh high output voltage (2) p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 oh = ? 200 a v cc1 ? 0.3 v cc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i oh = ? 200 a v cc2 ? 0.3 v cc2 v oh high output voltage xout highpower i oh = ? 1ma v cc1 ? 2.0 v cc1 v lowpower i oh = ? 0.5ma v cc1 ? 2.0 v cc1 high output voltage xc out highpower with no load applied 2.5 v lowpower with no load applied 1.6 v ol low output voltage (2) p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i ol =5ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i ol =5ma 2.0 v ol low output voltage (2) p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 i ol =200 a 0.45 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 i ol =200 a 0.45 v ol low output voltage xout highpower i ol =1ma 2.0 v lowpower i ol =0.5ma 2.0 low output voltage xcout highpower with no load applied 0 v lowpower with no load applied 0 v t+- v t- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int5 , nmi , adtrg , cts0 to cts2 , clk0 to clk4, ta0out to ta4out, ki0 to ki3 , rxd0 to rxd2, scl0 to scl2, sda0 to sda2, sin3, sin4 0.2 1.0 v v t+- v t- hysteresis reset 0.2 2.5 v i ih high input current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, xin, reset , cnvss, byte v i =5v 5.0 a i il low input current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7,p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, xin, reset , cnvss, byte v i =0v ? 5.0 a r pullup pull-up resistance (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7,p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 v i =0v 30 50 170 k ? r fxin feedback resistance xin 1.5 m ? r fxcin feedback resistance xcin 15 m ? v ram ram retention voltage at stop mode 2.0 v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 88 of 96 rej03b0001-0241 notes: 1. referenced to v cc1 =v cc2 =4.0 to 5.5v, v ss = 0v at t opr = ? 40 to 85 c / ? 40 to 125 c, f(bclk)=24mhz unless otherwise specified. t version = ? 40 to 85 c, v version = ? 40 to 125 c. 2. with one timer operated using fc32. 3. this indicates the memory in whic h the program to be executed exists. table 5.58 electrical characteristics (2) (1) symbol parameter measuring condition standard unit min. typ. max. i cc power supply current (v cc1 =v cc2 =4.0v to 5.5v) in single-chip mode, the output pins are open and other pins are v ss mask rom f(bclk)=24mhz no division, pll operation 14 20 ma no division, on-chip oscillation 1ma flash memory f(bclk)=24mhz, no division, pll operation 18 27 ma no division, on-chip oscillation 1.8 ma flash memory program f(bclk)=10mhz, v cc1 =5.0v 15 ma flash memory erase f(bclk)=10mhz, v cc1 =5.0v 25 ma mask rom f(xcin)=32khz low power dissipation mode, rom (3) 25 a flash memory f(bclk)=32khz low power dissipation mode, ram (3) 25 a f(bclk)=32khz low power dissipation mode, flash memory (3) 420 a on-chip oscillation, wait mode 50 a mask rom flash memory f(bclk)=32khz wait mode (2) , oscillation capability high 7.5 a f(bclk)=32khz wait mode (2) , oscillation capability low 2.0 a stop mode topr =25 c 2.0 6.0 a stop mode topr =85 c 20 a stop mode topr =125 c tbd a m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 89 of 96 rej03b0001-0241 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 40 to 85 c (t version) / ? 40 to 125 c (v version) unless otherwise specified) table 5.59 external clock input (xin input) symbol parameter standard unit min. max. t c external clock input cycle time 62.5 ns t w(h) external clock input high pulse width 25 ns t w(l) external clock input low pulse width 25 ns t r external clock rise time 15 ns t f external clock fall time 15 ns m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 90 of 96 rej03b0001-0241 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 40 to 85 c (t version) / ? 40 to 125 c (v version) unless otherwise specified) table 5.60 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 100 ns t w(tah) taiin input high pulse width 40 ns t w(tal) taiin input low pulse width 40 ns table 5.61 timer a input (gating input in timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 400 ns t w(tah) taiin input high pulse width 200 ns t w(tal) taiin input low pulse width 200 ns table 5.62 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 200 ns t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns table 5.63 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns table 5.64 timer a input (counter increment/ decrement input in event counter mode) symbol parameter standard unit min. max. t c(up) taiout input cycle time 2000 ns t w(uph) taiout input high pulse width 1000 ns t w(upl) taiout input low pulse width 1000 ns t su(up-tin) taiout input setup time 400 ns t h(tin-up) taiout input hold time 400 ns table 5.65 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 800 ns t su(tain-taout) taiout input setup time 200 ns t su(taout-tain) taiin input setup time 200 ns m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 91 of 96 rej03b0001-0241 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 40 to 85 c (t version) / ? 40 to 125 c (v version) unless otherwise specified) table 5.66 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time (counted on one edge) 100 ns t w(tbh) tbiin input high pulse width (counted on one edge) 40 ns t w(tbl) tbiin input low pulse width (counted on one edge) 40 ns t c(tb) tbiin input cycle time (counted on both edges) 200 ns t w(tbh) tbiin input high pulse width (counted on both edges) 80 ns t w(tbl) tbiin input low pulse width (counted on both edges) 80 ns table 5.67 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns table 5.68 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns table 5.69 a/d trigger input symbol parameter standard unit min. max. t c(ad) adtrg input cycle time 1000 ns t w(adl) adtrg input low pulse width 125 ns table 5.70 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ns t w(ckh) clki input high pulse width 100 ns t w(ckl) clki input low pulse width 100 ns t d(c-q) txdi output delay time 80 ns t h(c-q) txdi hold time 0 ns t su(d-c) rxdi input setup time 70 ns t h(c-d) rxdi input hold time 90 ns table 5.71 external interrupt inti input symbol parameter standard unit min. max. t w(inh) inti input high pulse width 250 ns t w(inl) inti input low pulse width 250 ns m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 92 of 96 rej03b0001-0241 v cc1 =v cc2 =5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 40 to 85 c (t version) / ? 40 to 125 c (v version) unless otherwise specified) figure 5.23 ports p0 to p10 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 93 of 96 rej03b0001-0241 figure 5.24 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) 5. electrical characteristics rev.2.41 jan 10, 2006 page 94 of 96 rej03b0001-0241 figure 5.25 timing diagram (2) t su(d-c) clk i txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) v cc1 =v cc2 =5v m16c/62p group (m16c/62p, m16c/62p t) appendix 1. package dimensions rev.2.41 jan 10, 2006 page 95 of 96 rej03b0001-0241 appendix 1.package dimensions 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. detailf l 1 c a a 1 a 2 l index mark y x f 1 38 39 64 65 102 103 128 * 1 * 3 * 2 z e z d d h d e h e b p l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.125 0.2 a 1.7 15.8 16.0 16.2 21.8 22.0 22.2 a 2 1.4 e 13.9 14.0 14.1 d 19.9 20.0 20.1 reference symbol dimension in millimeters min nom max 0.17 0.22 0.27 0.09 0.145 0.20 0.10 0.75 0.75 0.20 0.125 1.0 p-lqfp128-14x20-0.50 0.9g mass[typ.] 128p6q-a plqp0128kb-a renesas code jeita package code previous code terminal cross section c bp c 1 b 1 e 0.8 0.5 0.825 0.575 z e z d b p a 1 h e h d y 0.10 e 0.65 c 0 10 l 0.4 0.6 0.8 0 0.1 0.2 a 3.05 16.5 16.8 17.1 22.5 22.8 23.1 a 2 2.8 e 13.814.014.2 d 19.8 20.0 20.2 reference symbol dimension in millimeters min nom max 0.25 0.3 0.4 0.13 0.15 0.2 p-qfp100-14x20-0.65 1.6g mass[typ.] 100p6s-a prqp0100jb-a renesas code jeita package code previous code y index mark 100 81 80 51 50 31 30 1 f * 2 * 1 * 3 z e z d e b p a h d d e h e c detail f a 1 a 2 l include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. m16c/62p group (m16c/62p, m16c/62p t) appendix 1. package dimensions rev.2.41 jan 10, 2006 page 96 of 96 rej03b0001-0241 terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y0.08 e0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.914.014.1 d 13.914.014.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e * 3 * 2 * 1 80 61 60 41 40 21 20 1 f index mark y z e z d c b p e a e h e d h d detail f l a 2 a 1 include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. 0.8 0.5 0.825 0.825 z e z d previous code jeita package code renesas code prqp0080ja-a 80p6s-a mass[typ.] 1.1g p-qfp80-14x14-0.65 0.2 0.15 0.13 0.4 0.3 0.25 max nom min dimension in millimeters symbol reference 14.2 14.0 13.8 d 14.2 14.0 13.8 e 2.8 a 2 17.1 16.8 16.5 17.1 16.8 16.5 3.05 a 0.2 0.1 0 0.8 0.6 0.4 l 10 0 c 0.65 e 0.10 y h d h e a 1 b p c - 1 revision history m16c/62p group (m16c/62p, m16c/62pt) hardware manual rev. date description page summary 1.10 may 28, 2003 1 applications are partly revised. 2 table 1.1.1 is partly revised. 4-5 table 1.1.2 and 1.1.3 is partly revised. ?note 1? is partly revised. 22 23 table 1.5.3 is partly revised. table 1.5.5 is partly revised. table 1.5.6 is added. 24 30 31 table 1.5.9 is partly revised. notes 1 and 2 in table 1.5.26 is partly revised. notes 1 in table 1.5.27 is partly revised. 30-31 note 3 is added to ?data output hold ti me (refers to bclk)? in table 1.5.26 and 1.5.27. 32 note 4 is added to ?th(ale-ad)? in table 1.5.28. 30-32 36-39 40-41 42 switching characteristi cs is partly revised. th(wr-ad) and th(wr-db) in figure 1.5.5 to 1.5.8 is partly revised. th(ale-ad), th(wr-cs), th(wr-db) and th(wr-ad) in figure 1.5.9 to 1.5.10 is partly revised. note 2 is added to table 1.5.29. 47 48 47-48 notes 1 and 2 in table 1. 5.45 is partly revised. notes 1 in table 1.5.46 is partly revised. note 3 is added to ?data output hold time (refers to bclk)? in table 1.5.45 and 1.5.46. 49 47-48 53-56 57-58 note 4 is added to ?th(ale-ad)? in table 1.5.47. switching characteristi cs is partly revised. th(wr-ad) and th(wr-db) in figure 1. 5.15 to 1.5.18 is partly revised. th(ale-ad), th(wr-cs), th(wr-db) and th(wr-ad) in figure 1.5.19 to 1.5.20 is partly revised. 2.00 oct 29, 2003 - since high reliability version is added, a group name is revised. m16c/62 group (m16c/62p) m16c/62 group (m16c/62p, m16c/62pt) 2-4 table 1.1 to 1.3 are revised. note 3 is partly revised. 2-4 6 7-9 11 12-15 17,19 18,20 30 31-32 table 1.1 to 1.3 are revised. note 3 is partly revised. figure 1.2 note5 is deleted. table 1.4 to 1.7 product list is partly revised. table 1.8 and figure 1.4 are added. figure 1.5 to 1.9 zp is added. table 1.10 and 1.12 zp is added to timer a. table 1.11 and 1.13 vcc1 is added to vref. table 5.1 is revised. table 5.2 and 5.3 are revised. c - 2 revision history m16c/62p group (m16c/62p, m16c/62pt) hardware manual 33 34,74 36 38,55 41 41-43, 58-60 44 table 5.4 a-d conversion ch aracteristics is revised. table 5.5 d-a conversion characteristics revised. table 5.6 to 5.7 and table 5.54 to 5.55 are revised. table 5.11 is revised. table 5.14 and 5.33 hlda output deley time is deleted. figure 5.1 is partly revised. table 5.27 to 5.29 and table 5.46 to 48 hlda output deley time is added. figure 5.2 timing diagram (1) xin input is added. 47-48 49-50 52 53 58 61 64-65 66-67 69 70-85 figure 5.5 to 5.6 read timing db dbi figure 5.7 to 5.8 write timing db dbi figure 5.10 db dbi table 5.30 is revised. figure 5.11 is partly revised. figure 5.12 timing diagram (1) xin input is added. figure 5.15 to 5.16 read timing db dbi figure 5.17 to 5.18 write timing db dbi figure 5.20 db dbi electrical characteristics (m16c/62pt) is added. 2.10 nov 07, 2003 8-9 23 table 1.5 to 1.7 product list is pa rtly revised. note 1 is deleted. table 3.1 is revised. 71 72 table 5.50 is revised. table 5.51 is deleted. 2.11 jan 06, 2004 16 17-18 table 1.9 note 3 vcc1 vcc2 vcc1 > vcc2 table 1.10 to 1.11 note 1 vcc1 vcc2 vcc1 > vcc2 31 table 5.2 power supply ripple allowable frequency unit mhz khz 2.30 sep 01, 2004 12 18, 20 19,21 24 table 1.9 and figure 1.5 are added. table 1.11 to 1.13 are revised. table 1.12 to 1.14 are revised. figure 3.1 is partly revised. 25 33 34 35 37 note 3 is added. note 6 is added. table 5.3 is revised. note 2 in table 5.4 is added. table 5.5 to 5.6 is partly revised. table 5.8 is revised. table 5.9 is revised. table 5.11 is revised. rev. date description page summary c - 3 revision history m16c/62p group (m16c/62p, m16c/62pt) hardware manual 40 57 70 72 73 74 76 79 table 5.24 is partly revised. table 5.43 is partly revised. table 5.48 is partly revised. table 5.50 is partly revised. table 5.53 is partly revised. table 5.55 is revised. table 5.57 is partly revised. table 5.69 is partly revised. 2.41 jan 01, 2006 - voltage down detection reset -> brown-out detection reset 2-4 tables 1.1 to 1.3 performance outline of m16c/62p group are partly revised. 7 table 1.4 product list (1) is partly revised. note 1 is added. 8 table 1.5 product list (2) is partly revised. note 1, 2 and 3 are added. 9 table 1.6 product list (3) is partly revised. note 1 and 2 are added. 10 table 1.7 product list (4) is partly revised. note 1 and 2 are added. 11 figure 1.3 type no., memory size, shows ram capacity, and package is partly revised 12 table 1.8 product code of flash memory version and romless version for m16c/62p is partly revised. 13 table 1.9 product code of flash memo ry version for m16c/62p is partly revised. 14 figure 1.6 pin configuration (top view) is partly revised. 15-17 tables 1.10 to 1.12 pin characteristics for 128-pin package are added. 18-19 figure 1.7 and 1.8 pin configur ation (top view) are partly revised. 20-21 tables 1.13 to 1.14 pin characteristics for 100-pin package are added. 22 figure 1.9 pin configuration (top view) is partly revised. 23-24 tables 1.15 to 1.16 pin characteristics for 80-pin package are added. 25-29 tables 1.17 to 1.21 are partly revised. 34 note 4 of table 4.1 sfr information is partly revised. 43 table 5.4 a/d conversion char acteristics is partly revised. 45 table 5.6 flash memory version elec trical characteristics for 100 cycle products is partly revised. table 5.7 flash memory version electrical characteristics for 10,000 cycle products is partly revised. table 5.8 flash memory version pr ogram / erase voltage and read operation voltage characteri stics is partly revised. 46 table 5.9 low voltage detection circuit electrical characteristics is partly revised. rev. date description page summary c - 4 revision history m16c/62p group (m16c/62p, m16c/62pt) hardware manual rev. date description page summary 47 figure 5.1 power supply circuit ti ming diagram is partly revised. 48 table 5.11 electrical characte ristics (1) is partly deleted. 49 table 5.12 electrical characte ristics (2) is partly revised. 50 note 1 of table 5.13 external clock input (xin input) is added. 67 notes 1 to 4 of table 5.32 external clock input (xin input) are added. 85 table 5.53 flash memory version elec trical characteristics for 100 cycle products is partly revised. st andard (min.) is partly revised. table 5.54 flash memory version elec trical characteristics for 10,000 cycle products is partly revised. st andard (min.) is partly revised. note 5 is revised. table 23.55 flash memory version program / erase voltage and read operation voltage characteri stics is partly revised. 87 table 5.57 electrical characte ristics (1) is partly deleted. 88 table 5.58 electrical charac teristics is partly revised. keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. 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also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or 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u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. unit2607 ruijing building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> 2-796-3115, fax: <82> 2-796-2145 renesas technology malaysia sdn. bhd. unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 20 0 6 . r e nesas technology cor p ., all rights rese r ved. printed in j a pan. colophon .3.0 |
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